Commit 14ef9d04 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch 'kvm-arm64/hyp-pcpu' into kvmarm-master/next 



Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents 2e02cbb2 816c347f

arch/arm64/Kconfig

+0 −26
Original line number Diff line number Diff line
@@ -1165,32 +1165,6 @@ config UNMAP_KERNEL_AT_EL0 


	  If unsure, say Y.



config HARDEN_BRANCH_PREDICTOR

	bool "Harden the branch predictor against aliasing attacks" if EXPERT

	default y

	help

	  Speculation attacks against some high-performance processors rely on

	  being able to manipulate the branch predictor for a victim context by

	  executing aliasing branches in the attacker context.  Such attacks

	  can be partially mitigated against by clearing internal branch

	  predictor state and limiting the prediction logic in some situations.



	  This config option will take CPU-specific actions to harden the

	  branch predictor against aliasing attacks and may rely on specific

	  instruction sequences or control bits being set by the system

	  firmware.



	  If unsure, say Y.



config ARM64_SSBD

	bool "Speculative Store Bypass Disable" if EXPERT

	default y

	help

	  This enables mitigation of the bypassing of previous stores

	  by speculative loads.



	  If unsure, say Y.



config RODATA_FULL_DEFAULT_ENABLED

	bool "Apply r/o permissions of VM areas also to their linear aliases"

	default y

arch/arm64/include/asm/assembler.h

+19 −10
Original line number Diff line number Diff line
@@ -218,6 +218,23 @@ lr .req x30 // link register 
	str	\src, [\tmp, :lo12:\sym]

	.endm



	/*

	 * @dst: destination register

	 */

#if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__)

	.macro	this_cpu_offset, dst

	mrs	\dst, tpidr_el2

	.endm

#else

	.macro	this_cpu_offset, dst

alternative_if_not ARM64_HAS_VIRT_HOST_EXTN

	mrs	\dst, tpidr_el1

alternative_else

	mrs	\dst, tpidr_el2

alternative_endif

	.endm

#endif



	/*

	 * @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP)

	 * @sym: The name of the per-cpu variable
@@ -226,11 +243,7 @@ lr .req x30 // link register 
	.macro adr_this_cpu, dst, sym, tmp

	adrp	\tmp, \sym

	add	\dst, \tmp, #:lo12:\sym

alternative_if_not ARM64_HAS_VIRT_HOST_EXTN

	mrs	\tmp, tpidr_el1

alternative_else

	mrs	\tmp, tpidr_el2

alternative_endif

	this_cpu_offset \tmp

	add	\dst, \dst, \tmp

	.endm
@@ -241,11 +254,7 @@ alternative_endif 
	 */

	.macro ldr_this_cpu dst, sym, tmp

	adr_l	\dst, \sym

alternative_if_not ARM64_HAS_VIRT_HOST_EXTN

	mrs	\tmp, tpidr_el1

alternative_else

	mrs	\tmp, tpidr_el2

alternative_endif

	this_cpu_offset \tmp

	ldr	\dst, [\dst, \tmp]

	.endm

arch/arm64/include/asm/cpucaps.h

+2 −2
Original line number Diff line number Diff line
@@ -31,13 +31,13 @@ 
#define ARM64_HAS_DCPOP				21

#define ARM64_SVE				22

#define ARM64_UNMAP_KERNEL_AT_EL0		23

#define ARM64_HARDEN_BRANCH_PREDICTOR		24

#define ARM64_SPECTRE_V2			24

#define ARM64_HAS_RAS_EXTN			25

#define ARM64_WORKAROUND_843419			26

#define ARM64_HAS_CACHE_IDC			27

#define ARM64_HAS_CACHE_DIC			28

#define ARM64_HW_DBM				29

#define ARM64_SSBD				30

#define ARM64_SPECTRE_V4			30

#define ARM64_MISMATCHED_CACHE_TYPE		31

#define ARM64_HAS_STAGE2_FWB			32

#define ARM64_HAS_CRC32				33

arch/arm64/include/asm/cpufeature.h

+0 −24
Original line number Diff line number Diff line
@@ -698,30 +698,6 @@ static inline bool system_supports_tlb_range(void) 
		cpus_have_const_cap(ARM64_HAS_TLB_RANGE);

}



#define ARM64_BP_HARDEN_UNKNOWN		-1

#define ARM64_BP_HARDEN_WA_NEEDED	0

#define ARM64_BP_HARDEN_NOT_REQUIRED	1



int get_spectre_v2_workaround_state(void);



#define ARM64_SSBD_UNKNOWN		-1

#define ARM64_SSBD_FORCE_DISABLE	0

#define ARM64_SSBD_KERNEL		1

#define ARM64_SSBD_FORCE_ENABLE		2

#define ARM64_SSBD_MITIGATED		3



static inline int arm64_get_ssbd_state(void)

{

#ifdef CONFIG_ARM64_SSBD

	extern int ssbd_state;

	return ssbd_state;

#else

	return ARM64_SSBD_UNKNOWN;

#endif

}



void arm64_set_ssbd_mitigation(bool state);



extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);



static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)

arch/arm64/include/asm/hyp_image.h

0 → 100644
+36 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2020 Google LLC.

 * Written by David Brazdil <dbrazdil@google.com>

 */



#ifndef __ARM64_HYP_IMAGE_H__

#define __ARM64_HYP_IMAGE_H__



/*

 * KVM nVHE code has its own symbol namespace prefixed with __kvm_nvhe_,

 * to separate it from the kernel proper.

 */

#define kvm_nvhe_sym(sym)	__kvm_nvhe_##sym



#ifdef LINKER_SCRIPT



/*

 * KVM nVHE ELF section names are prefixed with .hyp, to separate them

 * from the kernel proper.

 */

#define HYP_SECTION_NAME(NAME)	.hyp##NAME



/* Defines an ELF hyp section from input section @NAME and its subsections. */

#define HYP_SECTION(NAME) \

	HYP_SECTION_NAME(NAME) : { *(NAME NAME##.*) }



/*

 * Defines a linker script alias of a kernel-proper symbol referenced by

 * KVM nVHE hyp code.

 */

#define KVM_NVHE_ALIAS(sym)	kvm_nvhe_sym(sym) = sym;



#endif /* LINKER_SCRIPT */



#endif /* __ARM64_HYP_IMAGE_H__ */