Commit 14ac09a6 authored by Christoph Hellwig's avatar Christoph Hellwig Committed by Thomas Bogendoerfer
Browse files

MIPS: refactor the runtime coherent vs noncoherent DMA indicators 



Replace the global coherentio enum, and the hw_coherentio (fake) boolean
variables with a single boolean dma_default_coherent flag.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 3440caf5

arch/mips/alchemy/common/setup.c

+1 −2
Original line number Diff line number Diff line
@@ -65,8 +65,7 @@ void __init plat_mem_setup(void) 
		/* Clear to obtain best system bus performance */

		clear_c0_config(1 << 19); /* Clear Config[OD] */



	coherentio = alchemy_dma_coherent() ?

		IO_COHERENCE_ENABLED : IO_COHERENCE_DISABLED;

	dma_default_coherent = alchemy_dma_coherent();



	board_setup();	/* board specific setup */

arch/mips/include/asm/dma-coherence.h

+4 −20
Original line number Diff line number Diff line
@@ -9,30 +9,14 @@ 
#ifndef __ASM_DMA_COHERENCE_H

#define __ASM_DMA_COHERENCE_H



enum coherent_io_user_state {

	IO_COHERENCE_DEFAULT,

	IO_COHERENCE_ENABLED,

	IO_COHERENCE_DISABLED,

};



#if defined(CONFIG_DMA_PERDEV_COHERENT)

/* Don't provide (hw_)coherentio to avoid misuse */

#elif defined(CONFIG_DMA_MAYBE_COHERENT)

extern enum coherent_io_user_state coherentio;

extern int hw_coherentio;



#ifdef CONFIG_DMA_MAYBE_COHERENT

extern bool dma_default_coherent;

static inline bool dev_is_dma_coherent(struct device *dev)

{

	return coherentio == IO_COHERENCE_ENABLED ||

		(coherentio == IO_COHERENCE_DEFAULT && hw_coherentio);

	return dma_default_coherent;

}

#else

#ifdef CONFIG_DMA_NONCOHERENT

#define coherentio	IO_COHERENCE_DISABLED

#else

#define coherentio	IO_COHERENCE_ENABLED

#define dma_default_coherent	(!IS_ENABLED(CONFIG_DMA_NONCOHERENT))

#endif

#define hw_coherentio	0

#endif /* CONFIG_DMA_MAYBE_COHERENT */



#endif

arch/mips/kernel/setup.c

+4 −6
Original line number Diff line number Diff line
@@ -803,14 +803,12 @@ arch_initcall(debugfs_mips); 
#endif



#ifdef CONFIG_DMA_MAYBE_COHERENT

/* User defined DMA coherency from command line. */

enum coherent_io_user_state coherentio = IO_COHERENCE_DEFAULT;

EXPORT_SYMBOL_GPL(coherentio);

int hw_coherentio;	/* Actual hardware supported DMA coherency setting. */

bool dma_default_coherent;

EXPORT_SYMBOL_GPL(dma_default_coherent);



static int __init setcoherentio(char *str)

{

	coherentio = IO_COHERENCE_ENABLED;

	dma_default_coherent = true;

	pr_info("Hardware DMA cache coherency (command line)\n");

	return 0;

}
@@ -818,7 +816,7 @@ early_param("coherentio", setcoherentio); 


static int __init setnocoherentio(char *str)

{

	coherentio = IO_COHERENCE_DISABLED;

	dma_default_coherent = true;

	pr_info("Software DMA cache coherency (command line)\n");

	return 0;

}

arch/mips/mm/c-r4k.c

+2 −6
Original line number Diff line number Diff line
@@ -1914,15 +1914,11 @@ void r4k_cache_init(void) 
	__local_flush_icache_user_range	= local_r4k_flush_icache_user_range;



#ifdef CONFIG_DMA_NONCOHERENT

#ifdef CONFIG_DMA_MAYBE_COHERENT

	if (coherentio == IO_COHERENCE_ENABLED ||

	    (coherentio == IO_COHERENCE_DEFAULT && hw_coherentio)) {

	if (dma_default_coherent) {

		_dma_cache_wback_inv	= (void *)cache_noop;

		_dma_cache_wback	= (void *)cache_noop;

		_dma_cache_inv		= (void *)cache_noop;

	} else

#endif /* CONFIG_DMA_MAYBE_COHERENT */

	{

	} else {

		_dma_cache_wback_inv	= r4k_dma_cache_wback_inv;

		_dma_cache_wback	= r4k_dma_cache_wback_inv;

		_dma_cache_inv		= r4k_dma_cache_inv;

arch/mips/mti-malta/malta-setup.c

+3 −3
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ static void __init plat_setup_iocoherency(void) 
		if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {

			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;

			pr_info("Enabled Bonito CPU coherency\n");

			hw_coherentio = 1;

			dma_default_coherent = true;

		}

		if (strstr(fw_getcmdline(), "iobcuncached")) {

			BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
@@ -118,12 +118,12 @@ static void __init plat_setup_iocoherency(void) 
		pr_info("CMP IOCU detected\n");

		cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));

		if (cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)

			hw_coherentio = 1;

			dma_default_coherent = true;

		else

			pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");

	}



	if (hw_coherentio)

	if (dma_default_coherent)

		pr_info("Hardware DMA cache coherency enabled\n");

	else

		pr_info("Software DMA cache coherency enabled\n");