Commit 147455ed authored by Emil Renner Berthing's avatar Emil Renner Berthing Committed by Conor Dooley
Browse files

clk: starfive: Rename "jh7100" to "jh71x0" for the common code 



Rename some variables from "jh7100" or "JH7100" to "jh71x0"
or "JH71X0".

Tested-by: default avatarTommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarEmil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: default avatarEmil Renner Berthing <kernel@esmil.dk>
Signed-off-by: default avatarHal Feng <hal.feng@starfivetech.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent e19aa786

drivers/clk/starfive/clk-starfive-jh7100-audio.c

+36 −36
Original line number Diff line number Diff line
@@ -28,66 +28,66 @@ 
#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD	(JH7100_AUDCLK_END + 6)

#define JH7100_AUDCLK_VAD_INTMEM                (JH7100_AUDCLK_END + 7)



static const struct jh7100_clk_data jh7100_audclk_data[] = {

	JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,

static const struct jh71x0_clk_data jh7100_audclk_data[] = {

	JH71X0__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,

		    JH7100_AUDCLK_AUDIO_SRC,

		    JH7100_AUDCLK_AUDIO_12288),

	JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,

	JH71X0__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,

		    JH7100_AUDCLK_AUDIO_SRC,

		    JH7100_AUDCLK_AUDIO_12288),

	JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,

	JH71X0_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH71X0_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,

		    JH7100_AUDCLK_ADC_MCLK,

		    JH7100_AUDCLK_I2SADC_BCLK_IOPAD),

	JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),

	JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,

	JH71X0__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),

	JH71X0_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,

		    JH7100_AUDCLK_I2SADC_BCLK_N,

		    JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,

		    JH7100_AUDCLK_I2SADC_BCLK),

	JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,

	JH71X0_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH71X0__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,

		    JH7100_AUDCLK_AUDIO_SRC,

		    JH7100_AUDCLK_AUDIO_12288),

	JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,

	JH71X0_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH71X0__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,

		    JH7100_AUDCLK_AUDIO_SRC,

		    JH7100_AUDCLK_AUDIO_12288),

	JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,

	JH71X0_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH71X0_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH71X0__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,

		    JH7100_AUDCLK_AUDIO_SRC,

		    JH7100_AUDCLK_AUDIO_12288),

	JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,

	JH71X0_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,

		    JH7100_AUDCLK_DAC_MCLK,

		    JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),

	JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),

	JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,

	JH71X0__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),

	JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,

		    JH7100_AUDCLK_I2S1_MCLK,

		    JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),

	JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,

	JH71X0_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH71X0_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,

		    JH7100_AUDCLK_I2S1_MCLK,

		    JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),

	JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),

	JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,

	JH71X0__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),

	JH71X0_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,

		    JH7100_AUDCLK_I2S1_BCLK_N,

		    JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),

	JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),

	JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),

	JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),

	JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),

	JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),

	JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),

	JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,

	JH71X0_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),

	JH71X0__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),

	JH71X0_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),

	JH71X0_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),

	JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),

	JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),

	JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),

	JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,

		    JH7100_AUDCLK_VAD_INTMEM,

		    JH7100_AUDCLK_AUDIO_12288),

};



static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)

{

	struct jh7100_clk_priv *priv = data;

	struct jh71x0_clk_priv *priv = data;

	unsigned int idx = clkspec->args[0];



	if (idx < JH7100_AUDCLK_END)
@@ -98,7 +98,7 @@ static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *d 


static int jh7100_audclk_probe(struct platform_device *pdev)

{

	struct jh7100_clk_priv *priv;

	struct jh71x0_clk_priv *priv;

	unsigned int idx;

	int ret;
@@ -117,12 +117,12 @@ static int jh7100_audclk_probe(struct platform_device *pdev) 
		struct clk_parent_data parents[4] = {};

		struct clk_init_data init = {

			.name = jh7100_audclk_data[idx].name,

			.ops = starfive_jh7100_clk_ops(max),

			.ops = starfive_jh71x0_clk_ops(max),

			.parent_data = parents,

			.num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,

			.num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,

			.flags = jh7100_audclk_data[idx].flags,

		};

		struct jh7100_clk *clk = &priv->reg[idx];

		struct jh71x0_clk *clk = &priv->reg[idx];

		unsigned int i;



		for (i = 0; i < init.num_parents; i++) {
@@ -140,7 +140,7 @@ static int jh7100_audclk_probe(struct platform_device *pdev) 


		clk->hw.init = &init;

		clk->idx = idx;

		clk->max_div = max & JH7100_CLK_DIV_MASK;

		clk->max_div = max & JH71X0_CLK_DIV_MASK;



		ret = devm_clk_hw_register(priv->dev, &clk->hw);

		if (ret)

drivers/clk/starfive/clk-starfive-jh7100.c

+196 −193

File changed.

Preview size limit exceeded, changes collapsed.

drivers/clk/starfive/clk-starfive-jh71x0.c

+141 −141
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * StarFive JH7100 Clock Generator Driver

 * StarFive JH71X0 Clock Generator Driver

 *

 * Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>

 */
@@ -12,27 +12,27 @@ 


#include "clk-starfive-jh71x0.h"



static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)

static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw)

{

	return container_of(hw, struct jh7100_clk, hw);

	return container_of(hw, struct jh71x0_clk, hw);

}



static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk)

static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk)

{

	return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]);

	return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]);

}



static u32 jh7100_clk_reg_get(struct jh7100_clk *clk)

static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk)

{

	struct jh7100_clk_priv *priv = jh7100_priv_from(clk);

	struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);

	void __iomem *reg = priv->base + 4 * clk->idx;



	return readl_relaxed(reg);

}



static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value)

static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value)

{

	struct jh7100_clk_priv *priv = jh7100_priv_from(clk);

	struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);

	void __iomem *reg = priv->base + 4 * clk->idx;

	unsigned long flags;
@@ -42,41 +42,41 @@ static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value) 
	spin_unlock_irqrestore(&priv->rmw_lock, flags);

}



static int jh7100_clk_enable(struct clk_hw *hw)

static int jh71x0_clk_enable(struct clk_hw *hw)

{

	struct jh7100_clk *clk = jh7100_clk_from(hw);

	struct jh71x0_clk *clk = jh71x0_clk_from(hw);



	jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE);

	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, JH71X0_CLK_ENABLE);

	return 0;

}



static void jh7100_clk_disable(struct clk_hw *hw)

static void jh71x0_clk_disable(struct clk_hw *hw)

{

	struct jh7100_clk *clk = jh7100_clk_from(hw);

	struct jh71x0_clk *clk = jh71x0_clk_from(hw);



	jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0);

	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, 0);

}



static int jh7100_clk_is_enabled(struct clk_hw *hw)

static int jh71x0_clk_is_enabled(struct clk_hw *hw)

{

	struct jh7100_clk *clk = jh7100_clk_from(hw);

	struct jh71x0_clk *clk = jh71x0_clk_from(hw);



	return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE);

	return !!(jh71x0_clk_reg_get(clk) & JH71X0_CLK_ENABLE);

}



static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw,

static unsigned long jh71x0_clk_recalc_rate(struct clk_hw *hw,

					    unsigned long parent_rate)

{

	struct jh7100_clk *clk = jh7100_clk_from(hw);

	u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK;

	struct jh71x0_clk *clk = jh71x0_clk_from(hw);

	u32 div = jh71x0_clk_reg_get(clk) & JH71X0_CLK_DIV_MASK;



	return div ? parent_rate / div : 0;

}



static int jh7100_clk_determine_rate(struct clk_hw *hw,

static int jh71x0_clk_determine_rate(struct clk_hw *hw,

				     struct clk_rate_request *req)

{

	struct jh7100_clk *clk = jh7100_clk_from(hw);

	struct jh71x0_clk *clk = jh71x0_clk_from(hw);

	unsigned long parent = req->best_parent_rate;

	unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);

	unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
@@ -102,232 +102,232 @@ static int jh7100_clk_determine_rate(struct clk_hw *hw, 
	return 0;

}



static int jh7100_clk_set_rate(struct clk_hw *hw,

static int jh71x0_clk_set_rate(struct clk_hw *hw,

			       unsigned long rate,

			       unsigned long parent_rate)

{

	struct jh7100_clk *clk = jh7100_clk_from(hw);

	struct jh71x0_clk *clk = jh71x0_clk_from(hw);

	unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),

				  1UL, (unsigned long)clk->max_div);



	jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);

	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, div);

	return 0;

}



static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw,

static unsigned long jh71x0_clk_frac_recalc_rate(struct clk_hw *hw,

						 unsigned long parent_rate)

{

	struct jh7100_clk *clk = jh7100_clk_from(hw);

	u32 reg = jh7100_clk_reg_get(clk);

	unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) +

			       ((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT);

	struct jh71x0_clk *clk = jh71x0_clk_from(hw);

	u32 reg = jh71x0_clk_reg_get(clk);

	unsigned long div100 = 100 * (reg & JH71X0_CLK_INT_MASK) +

			       ((reg & JH71X0_CLK_FRAC_MASK) >> JH71X0_CLK_FRAC_SHIFT);



	return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;

	return (div100 >= JH71X0_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;

}



static int jh7100_clk_frac_determine_rate(struct clk_hw *hw,

static int jh71x0_clk_frac_determine_rate(struct clk_hw *hw,

					  struct clk_rate_request *req)

{

	unsigned long parent100 = 100 * req->best_parent_rate;

	unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);

	unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),

				     JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);

				     JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);

	unsigned long result = parent100 / div100;



	/* clamp the result as in jh7100_clk_determine_rate() above */

	if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX)

	/* clamp the result as in jh71x0_clk_determine_rate() above */

	if (result > req->max_rate && div100 < JH71X0_CLK_FRAC_MAX)

		result = parent100 / (div100 + 1);

	if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN)

	if (result < req->min_rate && div100 > JH71X0_CLK_FRAC_MIN)

		result = parent100 / (div100 - 1);



	req->rate = result;

	return 0;

}



static int jh7100_clk_frac_set_rate(struct clk_hw *hw,

static int jh71x0_clk_frac_set_rate(struct clk_hw *hw,

				    unsigned long rate,

				    unsigned long parent_rate)

{

	struct jh7100_clk *clk = jh7100_clk_from(hw);

	struct jh71x0_clk *clk = jh71x0_clk_from(hw);

	unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),

				     JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);

	u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100);

				     JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);

	u32 value = ((div100 % 100) << JH71X0_CLK_FRAC_SHIFT) | (div100 / 100);



	jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value);

	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, value);

	return 0;

}



static u8 jh7100_clk_get_parent(struct clk_hw *hw)

static u8 jh71x0_clk_get_parent(struct clk_hw *hw)

{

	struct jh7100_clk *clk = jh7100_clk_from(hw);

	u32 value = jh7100_clk_reg_get(clk);

	struct jh71x0_clk *clk = jh71x0_clk_from(hw);

	u32 value = jh71x0_clk_reg_get(clk);



	return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT;

	return (value & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT;

}



static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index)

static int jh71x0_clk_set_parent(struct clk_hw *hw, u8 index)

{

	struct jh7100_clk *clk = jh7100_clk_from(hw);

	u32 value = (u32)index << JH7100_CLK_MUX_SHIFT;

	struct jh71x0_clk *clk = jh71x0_clk_from(hw);

	u32 value = (u32)index << JH71X0_CLK_MUX_SHIFT;



	jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value);

	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_MUX_MASK, value);

	return 0;

}



static int jh7100_clk_mux_determine_rate(struct clk_hw *hw,

static int jh71x0_clk_mux_determine_rate(struct clk_hw *hw,

					 struct clk_rate_request *req)

{

	return clk_mux_determine_rate_flags(hw, req, 0);

}



static int jh7100_clk_get_phase(struct clk_hw *hw)

static int jh71x0_clk_get_phase(struct clk_hw *hw)

{

	struct jh7100_clk *clk = jh7100_clk_from(hw);

	u32 value = jh7100_clk_reg_get(clk);

	struct jh71x0_clk *clk = jh71x0_clk_from(hw);

	u32 value = jh71x0_clk_reg_get(clk);



	return (value & JH7100_CLK_INVERT) ? 180 : 0;

	return (value & JH71X0_CLK_INVERT) ? 180 : 0;

}



static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees)

static int jh71x0_clk_set_phase(struct clk_hw *hw, int degrees)

{

	struct jh7100_clk *clk = jh7100_clk_from(hw);

	struct jh71x0_clk *clk = jh71x0_clk_from(hw);

	u32 value;



	if (degrees == 0)

		value = 0;

	else if (degrees == 180)

		value = JH7100_CLK_INVERT;

		value = JH71X0_CLK_INVERT;

	else

		return -EINVAL;



	jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value);

	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_INVERT, value);

	return 0;

}



#ifdef CONFIG_DEBUG_FS

static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)

static void jh71x0_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)

{

	static const struct debugfs_reg32 jh7100_clk_reg = {

	static const struct debugfs_reg32 jh71x0_clk_reg = {

		.name = "CTRL",

		.offset = 0,

	};

	struct jh7100_clk *clk = jh7100_clk_from(hw);

	struct jh7100_clk_priv *priv = jh7100_priv_from(clk);

	struct jh71x0_clk *clk = jh71x0_clk_from(hw);

	struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);

	struct debugfs_regset32 *regset;



	regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);

	if (!regset)

		return;



	regset->regs = &jh7100_clk_reg;

	regset->regs = &jh71x0_clk_reg;

	regset->nregs = 1;

	regset->base = priv->base + 4 * clk->idx;



	debugfs_create_regset32("registers", 0400, dentry, regset);

}

#else

#define jh7100_clk_debug_init NULL

#define jh71x0_clk_debug_init NULL

#endif



static const struct clk_ops jh7100_clk_gate_ops = {

	.enable = jh7100_clk_enable,

	.disable = jh7100_clk_disable,

	.is_enabled = jh7100_clk_is_enabled,

	.debug_init = jh7100_clk_debug_init,

static const struct clk_ops jh71x0_clk_gate_ops = {

	.enable = jh71x0_clk_enable,

	.disable = jh71x0_clk_disable,

	.is_enabled = jh71x0_clk_is_enabled,

	.debug_init = jh71x0_clk_debug_init,

};



static const struct clk_ops jh7100_clk_div_ops = {

	.recalc_rate = jh7100_clk_recalc_rate,

	.determine_rate = jh7100_clk_determine_rate,

	.set_rate = jh7100_clk_set_rate,

	.debug_init = jh7100_clk_debug_init,

static const struct clk_ops jh71x0_clk_div_ops = {

	.recalc_rate = jh71x0_clk_recalc_rate,

	.determine_rate = jh71x0_clk_determine_rate,

	.set_rate = jh71x0_clk_set_rate,

	.debug_init = jh71x0_clk_debug_init,

};



static const struct clk_ops jh7100_clk_fdiv_ops = {

	.recalc_rate = jh7100_clk_frac_recalc_rate,

	.determine_rate = jh7100_clk_frac_determine_rate,

	.set_rate = jh7100_clk_frac_set_rate,

	.debug_init = jh7100_clk_debug_init,

static const struct clk_ops jh71x0_clk_fdiv_ops = {

	.recalc_rate = jh71x0_clk_frac_recalc_rate,

	.determine_rate = jh71x0_clk_frac_determine_rate,

	.set_rate = jh71x0_clk_frac_set_rate,

	.debug_init = jh71x0_clk_debug_init,

};



static const struct clk_ops jh7100_clk_gdiv_ops = {

	.enable = jh7100_clk_enable,

	.disable = jh7100_clk_disable,

	.is_enabled = jh7100_clk_is_enabled,

	.recalc_rate = jh7100_clk_recalc_rate,

	.determine_rate = jh7100_clk_determine_rate,

	.set_rate = jh7100_clk_set_rate,

	.debug_init = jh7100_clk_debug_init,

static const struct clk_ops jh71x0_clk_gdiv_ops = {

	.enable = jh71x0_clk_enable,

	.disable = jh71x0_clk_disable,

	.is_enabled = jh71x0_clk_is_enabled,

	.recalc_rate = jh71x0_clk_recalc_rate,

	.determine_rate = jh71x0_clk_determine_rate,

	.set_rate = jh71x0_clk_set_rate,

	.debug_init = jh71x0_clk_debug_init,

};



static const struct clk_ops jh7100_clk_mux_ops = {

	.determine_rate = jh7100_clk_mux_determine_rate,

	.set_parent = jh7100_clk_set_parent,

	.get_parent = jh7100_clk_get_parent,

	.debug_init = jh7100_clk_debug_init,

static const struct clk_ops jh71x0_clk_mux_ops = {

	.determine_rate = jh71x0_clk_mux_determine_rate,

	.set_parent = jh71x0_clk_set_parent,

	.get_parent = jh71x0_clk_get_parent,

	.debug_init = jh71x0_clk_debug_init,

};



static const struct clk_ops jh7100_clk_gmux_ops = {

	.enable = jh7100_clk_enable,

	.disable = jh7100_clk_disable,

	.is_enabled = jh7100_clk_is_enabled,

	.determine_rate = jh7100_clk_mux_determine_rate,

	.set_parent = jh7100_clk_set_parent,

	.get_parent = jh7100_clk_get_parent,

	.debug_init = jh7100_clk_debug_init,

static const struct clk_ops jh71x0_clk_gmux_ops = {

	.enable = jh71x0_clk_enable,

	.disable = jh71x0_clk_disable,

	.is_enabled = jh71x0_clk_is_enabled,

	.determine_rate = jh71x0_clk_mux_determine_rate,

	.set_parent = jh71x0_clk_set_parent,

	.get_parent = jh71x0_clk_get_parent,

	.debug_init = jh71x0_clk_debug_init,

};



static const struct clk_ops jh7100_clk_mdiv_ops = {

	.recalc_rate = jh7100_clk_recalc_rate,

	.determine_rate = jh7100_clk_determine_rate,

	.get_parent = jh7100_clk_get_parent,

	.set_parent = jh7100_clk_set_parent,

	.set_rate = jh7100_clk_set_rate,

	.debug_init = jh7100_clk_debug_init,

static const struct clk_ops jh71x0_clk_mdiv_ops = {

	.recalc_rate = jh71x0_clk_recalc_rate,

	.determine_rate = jh71x0_clk_determine_rate,

	.get_parent = jh71x0_clk_get_parent,

	.set_parent = jh71x0_clk_set_parent,

	.set_rate = jh71x0_clk_set_rate,

	.debug_init = jh71x0_clk_debug_init,

};



static const struct clk_ops jh7100_clk_gmd_ops = {

	.enable = jh7100_clk_enable,

	.disable = jh7100_clk_disable,

	.is_enabled = jh7100_clk_is_enabled,

	.recalc_rate = jh7100_clk_recalc_rate,

	.determine_rate = jh7100_clk_determine_rate,

	.get_parent = jh7100_clk_get_parent,

	.set_parent = jh7100_clk_set_parent,

	.set_rate = jh7100_clk_set_rate,

	.debug_init = jh7100_clk_debug_init,

static const struct clk_ops jh71x0_clk_gmd_ops = {

	.enable = jh71x0_clk_enable,

	.disable = jh71x0_clk_disable,

	.is_enabled = jh71x0_clk_is_enabled,

	.recalc_rate = jh71x0_clk_recalc_rate,

	.determine_rate = jh71x0_clk_determine_rate,

	.get_parent = jh71x0_clk_get_parent,

	.set_parent = jh71x0_clk_set_parent,

	.set_rate = jh71x0_clk_set_rate,

	.debug_init = jh71x0_clk_debug_init,

};



static const struct clk_ops jh7100_clk_inv_ops = {

	.get_phase = jh7100_clk_get_phase,

	.set_phase = jh7100_clk_set_phase,

	.debug_init = jh7100_clk_debug_init,

static const struct clk_ops jh71x0_clk_inv_ops = {

	.get_phase = jh71x0_clk_get_phase,

	.set_phase = jh71x0_clk_set_phase,

	.debug_init = jh71x0_clk_debug_init,

};



const struct clk_ops *starfive_jh7100_clk_ops(u32 max)

const struct clk_ops *starfive_jh71x0_clk_ops(u32 max)

{

	if (max & JH7100_CLK_DIV_MASK) {

		if (max & JH7100_CLK_MUX_MASK) {

			if (max & JH7100_CLK_ENABLE)

				return &jh7100_clk_gmd_ops;

			return &jh7100_clk_mdiv_ops;

	if (max & JH71X0_CLK_DIV_MASK) {

		if (max & JH71X0_CLK_MUX_MASK) {

			if (max & JH71X0_CLK_ENABLE)

				return &jh71x0_clk_gmd_ops;

			return &jh71x0_clk_mdiv_ops;

		}

		if (max & JH7100_CLK_ENABLE)

			return &jh7100_clk_gdiv_ops;

		if (max == JH7100_CLK_FRAC_MAX)

			return &jh7100_clk_fdiv_ops;

		return &jh7100_clk_div_ops;

		if (max & JH71X0_CLK_ENABLE)

			return &jh71x0_clk_gdiv_ops;

		if (max == JH71X0_CLK_FRAC_MAX)

			return &jh71x0_clk_fdiv_ops;

		return &jh71x0_clk_div_ops;

	}



	if (max & JH7100_CLK_MUX_MASK) {

		if (max & JH7100_CLK_ENABLE)

			return &jh7100_clk_gmux_ops;

		return &jh7100_clk_mux_ops;

	if (max & JH71X0_CLK_MUX_MASK) {

		if (max & JH71X0_CLK_ENABLE)

			return &jh71x0_clk_gmux_ops;

		return &jh71x0_clk_mux_ops;

	}



	if (max & JH7100_CLK_ENABLE)

		return &jh7100_clk_gate_ops;

	if (max & JH71X0_CLK_ENABLE)

		return &jh71x0_clk_gate_ops;



	return &jh7100_clk_inv_ops;

	return &jh71x0_clk_inv_ops;

}

EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops);
 
EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops);

drivers/clk/starfive/clk-starfive-jh71x0.h

+45 −36

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