Commit 14615ecc authored by John David Anglin's avatar John David Anglin Committed by Helge Deller
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parisc: Simplify fast path for non-access data TLB faults 



With the latest cache fix for non-access faults and the support for
non-access faults (code 17) in handle_interruption, we can remove
the fast path emulation for fdc, fic, pdc, lpa, probe and probei
instructions.

Signed-off-by: default avatarJohn David Anglin <dave.anglin@bell.net>
Signed-off-by: default avatarHelge Deller <deller@gmx.de>
parent e00b0a2a

arch/parisc/kernel/entry.S

+5 −67
Original line number Diff line number Diff line
@@ -1288,74 +1288,12 @@ nadtlb_check_alias_20: 
nadtlb_emulate:



	/*

	 * Non access misses can be caused by fdc,fic,pdc,lpa,probe and

	 * probei instructions. We don't want to fault for these

	 * instructions (not only does it not make sense, it can cause

	 * deadlocks, since some flushes are done with the mmap

	 * semaphore held). If the translation doesn't exist, we can't

	 * insert a translation, so have to emulate the side effects

	 * of the instruction. Since we don't insert a translation

	 * we can get a lot of faults during a flush loop, so it makes

	 * sense to try to do it here with minimum overhead. We only

	 * emulate fdc,fic,pdc,probew,prober instructions whose base 

	 * and index registers are not shadowed. We defer everything 

	 * else to the "slow" path.

	 * Non-access misses can be caused by fdc,fic,pdc,lpa,probe and

	 * probei instructions. The kernel no longer faults doing flushes.

	 * Use of lpa and probe instructions is rare. Given the issue

	 * with shadow registers, we defer everything to the "slow" path.

	 */



	mfctl           %cr19,%r9 /* Get iir */



	/* PA 2.0 Arch Ref. Book pg 382 has a good description of the insn bits.

	   Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */



	/* Checks for fdc,fdce,pdc,"fic,4f" only */

	ldi             0x280,%r16

	and             %r9,%r16,%r17

	cmpb,<>,n       %r16,%r17,nadtlb_probe_check

	bb,>=,n         %r9,26,nadtlb_nullify  /* m bit not set, just nullify */

	BL		get_register,%r25

	extrw,u         %r9,15,5,%r8           /* Get index register # */

	cmpib,COND(=),n        -1,%r1,nadtlb_fault    /* have to use slow path */

	copy            %r1,%r24

	BL		get_register,%r25

	extrw,u         %r9,10,5,%r8           /* Get base register # */

	cmpib,COND(=),n        -1,%r1,nadtlb_fault    /* have to use slow path */

	BL		set_register,%r25

	add,l           %r1,%r24,%r1           /* doesn't affect c/b bits */



nadtlb_nullify:

	mfctl           %ipsw,%r8

	ldil            L%PSW_N,%r9

	or              %r8,%r9,%r8            /* Set PSW_N */

	mtctl           %r8,%ipsw



	rfir

	nop



	/* 

		When there is no translation for the probe address then we

		must nullify the insn and return zero in the target register.

		This will indicate to the calling code that it does not have 

		write/read privileges to this address.



		This should technically work for prober and probew in PA 1.1,

		and also probe,r and probe,w in PA 2.0



		WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!

		THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.



	*/

nadtlb_probe_check:

	ldi             0x80,%r16

	and             %r9,%r16,%r17

	cmpb,<>,n       %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/

	BL              get_register,%r25      /* Find the target register */

	extrw,u         %r9,31,5,%r8           /* Get target register */

	cmpib,COND(=),n        -1,%r1,nadtlb_fault    /* have to use slow path */

	BL		set_register,%r25

	copy            %r0,%r1                /* Write zero to target register */

	b nadtlb_nullify                       /* Nullify return insn */

	nop



	b,n		nadtlb_fault



#ifdef CONFIG_64BIT

itlb_miss_20w: