Commit 143983e5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-5.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 

Pull dmaengine updates from Vinod Koul:
 "We have couple of drivers removed a new driver and bunch of new device
  support and few updates to drivers for this round.

  New drivers/devices:
   - Intel LGM SoC DMA driver
   - Actions Semi S500 DMA controller
   - Renesas r8a779a0 dma controller
   - Ingenic JZ4760(B) dma controller
   - Intel KeemBay AxiDMA controller

  Removed:
   - Coh901318 dma driver
   - Zte zx dma driver
   - Sirfsoc dma driver

  Updates:
   - mmp_pdma, mmp_tdma gained module support
   - imx-sdma become modern and dropped platform data support
   - dw-axi driver gained slave and cyclic dma support"

* tag 'dmaengine-5.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (58 commits)
  dmaengine: dw-axi-dmac: remove redundant null check on desc
  dmaengine: xilinx_dma: Alloc tx descriptors GFP_NOWAIT
  dmaengine: dw-axi-dmac: Virtually split the linked-list
  dmaengine: dw-axi-dmac: Set constraint to the Max segment size
  dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers
  dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake
  dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support
  dmaengine: drivers: Kconfig: add HAS_IOMEM dependency to DW_AXI_DMAC
  dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields
  dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
  dmaengine: dw-axi-dmac: Support burst residue granularity
  dmaengine: dw-axi-dmac: Support of_dma_controller_register()
  dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic()
  dmaengine: dw-axi-dmac: Support device_prep_slave_sg
  dmaengine: dw-axi-dmac: Add device_config operation
  dmaengine: dw-axi-dmac: Add device_synchronize() callback
  dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources()
  dmaengine: dw-axi-dmac: simplify descriptor management
  dt-bindings: dma: Add YAML schemas for dw-axi-dmac
  dmaengine: ti: k3-psil: optimize struct psil_endpoint_config for size
  ...
parents 628af439 eda38ce4

Documentation/admin-guide/kernel-parameters.txt

+6 −0
Original line number Diff line number Diff line
@@ -1674,6 +1674,12 @@ 
			In such case C2/C3 won't be used again.

			idle=nomwait: Disable mwait for CPU C-states



	idxd.sva=	[HW]

			Format: <bool>

			Allow force disabling of Shared Virtual Memory (SVA)

			support for the idxd driver. By default it is set to

			true (1).



	ieee754=	[MIPS] Select IEEE Std 754 conformance mode

			Format: { strict | legacy | 2008 | relaxed }

			Default: strict

Documentation/devicetree/bindings/dma/ingenic,dma.yaml

+2 −0
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ properties: 
    enum:

      - ingenic,jz4740-dma

      - ingenic,jz4725b-dma

      - ingenic,jz4760-dma

      - ingenic,jz4760b-dma

      - ingenic,jz4770-dma

      - ingenic,jz4780-dma

      - ingenic,x1000-dma

Documentation/devicetree/bindings/dma/intel,ldma.yaml

0 → 100644
+116 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/intel,ldma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Lightning Mountain centralized DMA controllers.



maintainers:

  - chuanhua.lei@intel.com

  - mallikarjunax.reddy@intel.com



allOf:

  - $ref: "dma-controller.yaml#"



properties:

  compatible:

    enum:

      - intel,lgm-cdma

      - intel,lgm-dma2tx

      - intel,lgm-dma1rx

      - intel,lgm-dma1tx

      - intel,lgm-dma0tx

      - intel,lgm-dma3

      - intel,lgm-toe-dma30

      - intel,lgm-toe-dma31



  reg:

    maxItems: 1



  "#dma-cells":

    const: 3

    description:

      The first cell is the peripheral's DMA request line.

      The second cell is the peripheral's (port) number corresponding to the channel.

      The third cell is the burst length of the channel.



  dma-channels:

    minimum: 1

    maximum: 16



  dma-channel-mask:

    maxItems: 1



  clocks:

    maxItems: 1



  resets:

    maxItems: 1



  reset-names:

    items:

      - const: ctrl



  interrupts:

    maxItems: 1



  intel,dma-poll-cnt:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      DMA descriptor polling counter is used to control the poling mechanism

      for the descriptor fetching for all channels.



  intel,dma-byte-en:

    type: boolean

    description:

      DMA byte enable is only valid for DMA write(RX).

      Byte enable(1) means DMA write will be based on the number of dwords

      instead of the whole burst.



  intel,dma-drb:

    type: boolean

    description:

      DMA descriptor read back to make sure data and desc synchronization.



  intel,dma-dburst-wr:

    type: boolean

    description:

      Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst;

      if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16.

      It only applies to RX DMA and memcopy DMA.



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    dma0: dma-controller@e0e00000 {

      compatible = "intel,lgm-cdma";

      reg = <0xe0e00000 0x1000>;

      #dma-cells = <3>;

      dma-channels = <16>;

      dma-channel-mask = <0xFFFF>;

      interrupt-parent = <&ioapic1>;

      interrupts = <82 1>;

      resets = <&rcu0 0x30 0>;

      reset-names = "ctrl";

      clocks = <&cgu0 80>;

      intel,dma-poll-cnt = <4>;

      intel,dma-byte-en;

      intel,dma-drb;

    };

  - |

    dma3: dma-controller@ec800000 {

      compatible = "intel,lgm-dma3";

      reg = <0xec800000 0x1000>;

      clocks = <&cgu0 71>;

      resets = <&rcu0 0x10 9>;

      #dma-cells = <3>;

      intel,dma-poll-cnt = <16>;

      intel,dma-byte-en;

      intel,dma-dburst-wr;

    };

Documentation/devicetree/bindings/dma/owl-dma.yaml

+4 −3
Original line number Diff line number Diff line
@@ -8,8 +8,8 @@ title: Actions Semi Owl SoCs DMA controller 


description: |

  The OWL DMA is a general-purpose direct memory access controller capable of

  supporting 10 and 12 independent DMA channels for S700 and S900 SoCs

  respectively.

  supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12

  independent DMA channels for the S500 and S900 SoC variants.



maintainers:

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
@@ -20,8 +20,9 @@ allOf: 
properties:

  compatible:

    enum:

      - actions,s900-dma

      - actions,s500-dma

      - actions,s700-dma

      - actions,s900-dma



  reg:

    maxItems: 1

Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml

+48 −28
Original line number Diff line number Diff line
@@ -14,7 +14,8 @@ allOf: 


properties:

  compatible:

    items:

    oneOf:

      - items:

          - enum:

              - renesas,dmac-r8a7742  # RZ/G1H

              - renesas,dmac-r8a7743  # RZ/G1M
@@ -40,8 +41,10 @@ properties: 
              - renesas,dmac-r8a77995 # R-Car D3

          - const: renesas,rcar-dmac



  reg:

    maxItems: 1

      - items:

          - const: renesas,dmac-r8a779a0 # R-Car V3U



  reg: true



  interrupts:

    minItems: 9
@@ -110,6 +113,23 @@ required: 
  - power-domains

  - resets



if:

  properties:

    compatible:

      contains:

        enum:

          - renesas,dmac-r8a779a0

then:

  properties:

    reg:

      items:

        - description: Base register block

        - description: Channel register block

else:

  properties:

    reg:

      maxItems: 1



additionalProperties: false



examples: