Commit 14341e76 authored by Srinivas Kandagatla's avatar Srinivas Kandagatla Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8450: add Soundwire and LPASS 



Add Soundwire controllers, Low Power Audio SubSystem (LPASS) devices and
LPASS pin controller.

Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Co-developed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221202152054.357316-3-krzysztof.kozlowski@linaro.org
parent 38463210

arch/arm64/boot/dts/qcom/sm8450.dtsi

+324 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <dt-bindings/interconnect/qcom,sm8450.h>

#include <dt-bindings/soc/qcom,gpr.h>

#include <dt-bindings/soc/qcom,rpmh-rsc.h>

#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>

#include <dt-bindings/thermal/thermal.h>



/ {
@@ -2098,6 +2099,209 @@ 
			};

		};



		wsa2macro: codec@31e0000 {

			compatible = "qcom,sm8450-lpass-wsa-macro";

			reg = <0 0x031e0000 0 0x1000>;

			clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&vamacro>;

			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";

			assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

					  <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

			assigned-clock-rates = <19200000>, <19200000>;



			#clock-cells = <0>;

			clock-output-names = "wsa2-mclk";

			pinctrl-names = "default";

			pinctrl-0 = <&wsa2_swr_active>;

			#sound-dai-cells = <1>;

		};



		/* WSA2 */

		swr4: soundwire-controller@31f0000 {

			compatible = "qcom,soundwire-v1.7.0";

			reg = <0 0x031f0000 0 0x2000>;

			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&wsa2macro>;

			clock-names = "iface";



			qcom,din-ports = <2>;

			qcom,dout-ports = <6>;



			qcom,ports-sinterval-low =	/bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;

			qcom,ports-offset1 =		/bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;

			qcom,ports-offset2 =		/bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;

			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;

			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			qcom,ports-lane-control =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;



			#address-cells = <2>;

			#size-cells = <0>;

			#sound-dai-cells = <1>;

		};



		rxmacro: codec@3200000 {

			compatible = "qcom,sm8450-lpass-rx-macro";

			reg = <0 0x3200000 0 0x1000>;

			clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&vamacro>;

			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";



			assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

					  <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

			assigned-clock-rates = <19200000>, <19200000>;



			#clock-cells = <0>;

			clock-output-names = "mclk";

			pinctrl-names = "default";

			pinctrl-0 = <&rx_swr_active>;

			#sound-dai-cells = <1>;

		};



		swr1: soundwire-controller@3210000 {

			compatible = "qcom,soundwire-v1.7.0";

			reg = <0 0x3210000 0 0x2000>;

			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rxmacro>;

			clock-names = "iface";

			label = "RX";

			qcom,din-ports = <0>;

			qcom,dout-ports = <5>;



			qcom,ports-sinterval-low =	/bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;

			qcom,ports-offset1 =		/bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;

			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;

			qcom,ports-hstart =		/bits/ 8 <0xff 0x03 0xff 0xff 0xff>;

			qcom,ports-hstop =		/bits/ 8 <0xff 0x06 0xff 0xff 0xff>;

			qcom,ports-word-length =	/bits/ 8 <0x01 0x07 0x04 0xff 0xff>;

			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0x00 0x01 0xff 0xff>;

			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0x00>;

			qcom,ports-lane-control =	/bits/ 8 <0x01 0x00 0x00 0x00 0x00>;



			#address-cells = <2>;

			#size-cells = <0>;

			#sound-dai-cells = <1>;

		};



		txmacro: codec@3220000 {

			compatible = "qcom,sm8450-lpass-tx-macro";

			reg = <0 0x3220000 0 0x1000>;

			clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&vamacro>;

			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";

			assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

					  <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

			assigned-clock-rates = <19200000>, <19200000>;



			#clock-cells = <0>;

			clock-output-names = "mclk";

			pinctrl-names = "default";

			pinctrl-0 = <&tx_swr_active>;

			#sound-dai-cells = <1>;

		};



		wsamacro: codec@3240000 {

			compatible = "qcom,sm8450-lpass-wsa-macro";

			reg = <0 0x03240000 0 0x1000>;

			clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&vamacro>;

			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";



			assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

					  <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

			assigned-clock-rates = <19200000>, <19200000>;



			#clock-cells = <0>;

			clock-output-names = "mclk";

			pinctrl-names = "default";

			pinctrl-0 = <&wsa_swr_active>;

			#sound-dai-cells = <1>;

		};



		/* WSA */

		swr0: soundwire-controller@3250000 {

			compatible = "qcom,soundwire-v1.7.0";

			reg = <0 0x03250000 0 0x2000>;

			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&wsamacro>;

			clock-names = "iface";



			qcom,din-ports = <2>;

			qcom,dout-ports = <6>;



			qcom,ports-sinterval-low =	/bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;

			qcom,ports-offset1 =		/bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;

			qcom,ports-offset2 =		/bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;

			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;

			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			qcom,ports-lane-control =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;



			#address-cells = <2>;

			#size-cells = <0>;

			#sound-dai-cells = <1>;

		};



		swr2: soundwire-controller@33b0000 {

			compatible = "qcom,soundwire-v1.7.0";

			reg = <0 0x33b0000 0 0x2000>;

			interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,

					      <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "core", "wake";



			clocks = <&vamacro>;

			clock-names = "iface";

			label = "TX";



			qcom,din-ports = <4>;

			qcom,dout-ports = <0>;

			qcom,ports-sinterval-low =	/bits/ 8 <0x01 0x01 0x03 0x03>;

			qcom,ports-offset1 =		/bits/ 8 <0x00 0x00 0x01 0x01>;

			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x00 0x00>;

			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff>;

			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff>;

			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff>;

			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0xff 0xff>;

			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff>;

			qcom,ports-lane-control =	/bits/ 8 <0x01 0x02 0x00 0x00>;



			#address-cells = <2>;

			#size-cells = <0>;

			#sound-dai-cells = <1>;

		};



		vamacro: codec@33f0000 {

			compatible = "qcom,sm8450-lpass-va-macro";

			reg = <0 0x033f0000 0 0x1000>;

			clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

			clock-names = "mclk", "macro", "dcodec", "npl";

			assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

			assigned-clock-rates = <19200000>;



			#clock-cells = <0>;

			clock-output-names = "fsgen";

			#sound-dai-cells = <1>;

		};



		remoteproc_adsp: remoteproc@30000000 {

			compatible = "qcom,sm8450-adsp-pas";

			reg = <0 0x30000000 0 0x100>;
@@ -3031,6 +3235,123 @@ 


		};



		lpass_tlmm: pinctrl@3440000{

			compatible = "qcom,sm8450-lpass-lpi-pinctrl";

			reg = <0 0x3440000 0x0 0x20000>,

			      <0 0x34d0000 0x0 0x10000>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&lpass_tlmm 0 0 23>;



			clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

			clock-names = "core", "audio";



			tx_swr_active: tx-swr-active-state {

				clk-pins {

					pins = "gpio0";

					function = "swr_tx_clk";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-disable;

				};



				data-pins {

					pins = "gpio1", "gpio2", "gpio14";

					function = "swr_tx_data";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-bus-hold;

				};

			};



			rx_swr_active: rx-swr-active-state {

				clk-pins {

					pins = "gpio3";

					function = "swr_rx_clk";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-disable;

				};



				data-pins {

					pins = "gpio4", "gpio5";

					function = "swr_rx_data";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-bus-hold;

				};

			};



			dmic01_default: dmic01-default-state {

				clk-pins {

					pins = "gpio6";

					function = "dmic1_clk";

					drive-strength = <8>;

					output-high;

				};



				data-pins {

					pins = "gpio7";

					function = "dmic1_data";

					drive-strength = <8>;

					input-enable;

				};

			};



			dmic02_default: dmic02-default-state {

				clk-pins {

					pins = "gpio8";

					function = "dmic2_clk";

					drive-strength = <8>;

					output-high;

				};



				data-pins {

					pins = "gpio9";

					function = "dmic2_data";

					drive-strength = <8>;

					input-enable;

				};

			};



			wsa_swr_active: wsa-swr-active-state {

				clk-pins {

					pins = "gpio10";

					function = "wsa_swr_clk";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-disable;

				};



				data-pins {

					pins = "gpio11";

					function = "wsa_swr_data";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-bus-hold;

				};

			};



			wsa2_swr_active: wsa2-swr-active-state {

				clk-pins {

					pins = "gpio15";

					function = "wsa2_swr_clk";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-disable;

				};



				data-pins {

					pins = "gpio16";

					function = "wsa2_swr_data";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-bus-hold;

				};

			};

		};



		apps_smmu: iommu@15000000 {

			compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";

			reg = <0 0x15000000 0 0x100000>;
@@ -3510,6 +3831,9 @@ 
		};

	};



	sound: sound {

	};



	thermal-zones {

		aoss0-thermal {

			polling-delay-passive = <0>;