Commit 142639a5 authored by Jonathan Marek's avatar Jonathan Marek Committed by Rob Clark
Browse files

drm/msm/a6xx: fix crashstate capture for A650 



A650 has a separate RSCC region, so dump RSCC registers separately, reading
them from the RSCC base. Without this change a GPU hang will cause a system
reset if CONFIG_DEV_COREDUMP is enabled.

Signed-off-by: default avatarJonathan Marek <jonathan@marek.ca>
Reviewed-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 62a35e81

drivers/gpu/drm/msm/adreno/a6xx_gmu.h

+5 −0
Original line number Diff line number Diff line
@@ -127,6 +127,11 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi) 
	readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \

		interval, timeout)



static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)

{

	return msm_readl(gmu->rscc + (offset << 2));

}



static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)

{

	return msm_writel(value, gmu->rscc + (offset << 2));

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

+18 −7
Original line number Diff line number Diff line
@@ -736,7 +736,8 @@ static void a6xx_get_ahb_gpu_registers(struct msm_gpu *gpu, 
static void _a6xx_get_gmu_registers(struct msm_gpu *gpu,

		struct a6xx_gpu_state *a6xx_state,

		const struct a6xx_registers *regs,

		struct a6xx_gpu_state_obj *obj)

		struct a6xx_gpu_state_obj *obj,

		bool rscc)

{

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
@@ -755,9 +756,17 @@ static void _a6xx_get_gmu_registers(struct msm_gpu *gpu, 
		u32 count = RANGE(regs->registers, i);

		int j;



		for (j = 0; j < count; j++)

			obj->data[index++] = gmu_read(gmu,

				regs->registers[i] + j);

		for (j = 0; j < count; j++) {

			u32 offset = regs->registers[i] + j;

			u32 val;



			if (rscc)

				val = gmu_read_rscc(gmu, offset);

			else

				val = gmu_read(gmu, offset);



			obj->data[index++] = val;

		}

	}

}
@@ -777,7 +786,9 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu, 


	/* Get the CX GMU registers from AHB */

	_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[0],

		&a6xx_state->gmu_registers[0]);

		&a6xx_state->gmu_registers[0], false);

	_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1],

		&a6xx_state->gmu_registers[1], true);



	if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu))

		return;
@@ -785,8 +796,8 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu, 
	/* Set the fence to ALLOW mode so we can access the registers */

	gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);



	_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1],

		&a6xx_state->gmu_registers[1]);

	_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[2],

		&a6xx_state->gmu_registers[2], false);

}



#define A6XX_GBIF_REGLIST_SIZE   1

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

+8 −4
Original line number Diff line number Diff line
@@ -341,10 +341,6 @@ static const u32 a6xx_gmu_cx_registers[] = { 
	0x5157, 0x5158, 0x515d, 0x515d, 0x5162, 0x5162, 0x5164, 0x5165,

	0x5180, 0x5186, 0x5190, 0x519e, 0x51c0, 0x51c0, 0x51c5, 0x51cc,

	0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201,

	/* GPU RSCC */

	0x8c8c, 0x8c8c, 0x8d01, 0x8d02, 0x8f40, 0x8f42, 0x8f44, 0x8f47,

	0x8f4c, 0x8f87, 0x8fec, 0x8fef, 0x8ff4, 0x902f, 0x9094, 0x9097,

	0x909c, 0x90d7, 0x913c, 0x913f, 0x9144, 0x917f,

	/* GMU AO */

	0x9300, 0x9316, 0x9400, 0x9400,

	/* GPU CC */
@@ -357,8 +353,16 @@ static const u32 a6xx_gmu_cx_registers[] = { 
	0xbc00, 0xbc16, 0xbc20, 0xbc27,

};



static const u32 a6xx_gmu_cx_rscc_registers[] = {

	/* GPU RSCC */

	0x008c, 0x008c, 0x0101, 0x0102, 0x0340, 0x0342, 0x0344, 0x0347,

	0x034c, 0x0387, 0x03ec, 0x03ef, 0x03f4, 0x042f, 0x0494, 0x0497,

	0x049c, 0x04d7, 0x053c, 0x053f, 0x0544, 0x057f,

};



static const struct a6xx_registers a6xx_gmu_reglist[] = {

	REGS(a6xx_gmu_cx_registers, 0, 0),

	REGS(a6xx_gmu_cx_rscc_registers, 0, 0),

	REGS(a6xx_gmu_gx_registers, 0, 0),

};