Commit 141bef44 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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memory: tegra: Consolidate registers definition into common header 



The Memory Controller registers definition is sparse and duplicated,
let's consolidate everything into a common place for consistency.

Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 77b7182f

drivers/memory/tegra/mc.c

+0 −30
Original line number Diff line number Diff line
@@ -19,36 +19,6 @@ 


#include "mc.h"



#define MC_INTSTATUS 0x000



#define MC_INTMASK 0x004



#define MC_ERR_STATUS 0x08

#define  MC_ERR_STATUS_TYPE_SHIFT 28

#define  MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT)

#define  MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT)

#define  MC_ERR_STATUS_READABLE (1 << 27)

#define  MC_ERR_STATUS_WRITABLE (1 << 26)

#define  MC_ERR_STATUS_NONSECURE (1 << 25)

#define  MC_ERR_STATUS_ADR_HI_SHIFT 20

#define  MC_ERR_STATUS_ADR_HI_MASK 0x3

#define  MC_ERR_STATUS_SECURITY (1 << 17)

#define  MC_ERR_STATUS_RW (1 << 16)



#define MC_ERR_ADR 0x0c



#define MC_GART_ERROR_REQ		0x30

#define MC_DECERR_EMEM_OTHERS_STATUS	0x58

#define MC_SECURITY_VIOLATION_STATUS	0x74



#define MC_EMEM_ARB_CFG 0x90

#define  MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x)	(((x) & 0x1ff) << 0)

#define  MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK	0x1ff

#define MC_EMEM_ARB_MISC0 0xd8



#define MC_EMEM_ADR_CFG 0x54

#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)



static const struct of_device_id tegra_mc_of_match[] = {

#ifdef CONFIG_ARCH_TEGRA_2x_SOC

	{ .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },

drivers/memory/tegra/mc.h

+47 −5
Original line number Diff line number Diff line
@@ -12,6 +12,37 @@ 


#include <soc/tegra/mc.h>



#define MC_INTSTATUS					0x00

#define MC_INTMASK					0x04

#define MC_ERR_STATUS					0x08

#define MC_ERR_ADR					0x0c

#define MC_GART_ERROR_REQ				0x30

#define MC_EMEM_ADR_CFG					0x54

#define MC_DECERR_EMEM_OTHERS_STATUS			0x58

#define MC_SECURITY_VIOLATION_STATUS			0x74

#define MC_EMEM_ARB_CFG					0x90

#define MC_EMEM_ARB_OUTSTANDING_REQ			0x94

#define MC_EMEM_ARB_TIMING_RCD				0x98

#define MC_EMEM_ARB_TIMING_RP				0x9c

#define MC_EMEM_ARB_TIMING_RC				0xa0

#define MC_EMEM_ARB_TIMING_RAS				0xa4

#define MC_EMEM_ARB_TIMING_FAW				0xa8

#define MC_EMEM_ARB_TIMING_RRD				0xac

#define MC_EMEM_ARB_TIMING_RAP2PRE			0xb0

#define MC_EMEM_ARB_TIMING_WAP2PRE			0xb4

#define MC_EMEM_ARB_TIMING_R2R				0xb8

#define MC_EMEM_ARB_TIMING_W2W				0xbc

#define MC_EMEM_ARB_TIMING_R2W				0xc0

#define MC_EMEM_ARB_TIMING_W2R				0xc4

#define MC_EMEM_ARB_DA_TURNS				0xd0

#define MC_EMEM_ARB_DA_COVERS				0xd4

#define MC_EMEM_ARB_MISC0				0xd8

#define MC_EMEM_ARB_MISC1				0xdc

#define MC_EMEM_ARB_RING1_THROTTLE			0xe0

#define MC_EMEM_ARB_OVERRIDE				0xe8

#define MC_TIMING_CONTROL_DBG				0xf8

#define MC_TIMING_CONTROL				0xfc



#define MC_INT_DECERR_MTS				BIT(16)

#define MC_INT_SECERR_SEC				BIT(13)

#define MC_INT_DECERR_VPR				BIT(12)
@@ -22,17 +53,28 @@ 
#define MC_INT_INVALID_GART_PAGE			BIT(7)

#define MC_INT_DECERR_EMEM				BIT(6)



#define MC_EMEM_ARB_OUTSTANDING_REQ			0x94

#define MC_ERR_STATUS_TYPE_SHIFT			28

#define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE		(0x6 << 28)

#define MC_ERR_STATUS_TYPE_MASK				(0x7 << 28)

#define MC_ERR_STATUS_READABLE				BIT(27)

#define MC_ERR_STATUS_WRITABLE				BIT(26)

#define MC_ERR_STATUS_NONSECURE				BIT(25)

#define MC_ERR_STATUS_ADR_HI_SHIFT			20

#define MC_ERR_STATUS_ADR_HI_MASK			0x3

#define MC_ERR_STATUS_SECURITY				BIT(17)

#define MC_ERR_STATUS_RW				BIT(16)



#define MC_EMEM_ADR_CFG_EMEM_NUMDEV			BIT(0)



#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x)		((x) & 0x1ff)

#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK		0x1ff



#define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK		0x1ff

#define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE	BIT(30)

#define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE	BIT(31)



#define MC_EMEM_ARB_OVERRIDE				0xe8

#define MC_EMEM_ARB_OVERRIDE_EACK_MASK			0x3



#define MC_TIMING_CONTROL_DBG				0xf8



#define MC_TIMING_CONTROL				0xfc

#define MC_TIMING_UPDATE				BIT(0)



static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset)

drivers/memory/tegra/tegra124.c

+0 −20
Original line number Diff line number Diff line
@@ -10,26 +10,6 @@ 


#include "mc.h"



#define MC_EMEM_ARB_CFG				0x90

#define MC_EMEM_ARB_OUTSTANDING_REQ		0x94

#define MC_EMEM_ARB_TIMING_RCD			0x98

#define MC_EMEM_ARB_TIMING_RP			0x9c

#define MC_EMEM_ARB_TIMING_RC			0xa0

#define MC_EMEM_ARB_TIMING_RAS			0xa4

#define MC_EMEM_ARB_TIMING_FAW			0xa8

#define MC_EMEM_ARB_TIMING_RRD			0xac

#define MC_EMEM_ARB_TIMING_RAP2PRE		0xb0

#define MC_EMEM_ARB_TIMING_WAP2PRE		0xb4

#define MC_EMEM_ARB_TIMING_R2R			0xb8

#define MC_EMEM_ARB_TIMING_W2W			0xbc

#define MC_EMEM_ARB_TIMING_R2W			0xc0

#define MC_EMEM_ARB_TIMING_W2R			0xc4

#define MC_EMEM_ARB_DA_TURNS			0xd0

#define MC_EMEM_ARB_DA_COVERS			0xd4

#define MC_EMEM_ARB_MISC0			0xd8

#define MC_EMEM_ARB_MISC1			0xdc

#define MC_EMEM_ARB_RING1_THROTTLE		0xe0



static const struct tegra_mc_client tegra124_mc_clients[] = {

	{

		.id = 0x00,

drivers/memory/tegra/tegra30.c

+0 −19
Original line number Diff line number Diff line
@@ -10,25 +10,6 @@ 


#include "mc.h"



#define MC_EMEM_ARB_CFG				0x90

#define MC_EMEM_ARB_OUTSTANDING_REQ		0x94

#define MC_EMEM_ARB_TIMING_RCD			0x98

#define MC_EMEM_ARB_TIMING_RP			0x9c

#define MC_EMEM_ARB_TIMING_RC			0xa0

#define MC_EMEM_ARB_TIMING_RAS			0xa4

#define MC_EMEM_ARB_TIMING_FAW			0xa8

#define MC_EMEM_ARB_TIMING_RRD			0xac

#define MC_EMEM_ARB_TIMING_RAP2PRE		0xb0

#define MC_EMEM_ARB_TIMING_WAP2PRE		0xb4

#define MC_EMEM_ARB_TIMING_R2R			0xb8

#define MC_EMEM_ARB_TIMING_W2W			0xbc

#define MC_EMEM_ARB_TIMING_R2W			0xc0

#define MC_EMEM_ARB_TIMING_W2R			0xc4

#define MC_EMEM_ARB_DA_TURNS			0xd0

#define MC_EMEM_ARB_DA_COVERS			0xd4

#define MC_EMEM_ARB_MISC0			0xd8

#define MC_EMEM_ARB_RING1_THROTTLE		0xe0



static const unsigned long tegra30_mc_emem_regs[] = {

	MC_EMEM_ARB_CFG,

	MC_EMEM_ARB_OUTSTANDING_REQ,