Commit 1417372f authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8350: move more nodes to correct place 



Continue ordering DT nodes by their address. Move RNG, UFS, system NoC
and SLPI nodes to the proper position.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230209133839.762631-4-dmitry.baryshkov@linaro.org
parent f5f6bd58

arch/arm64/boot/dts/qcom/sm8350.dtsi

+157 −157
Original line number Diff line number Diff line
@@ -1421,6 +1421,13 @@ 
			};

		};



		rng: rng@10d3000 {

			compatible = "qcom,prng-ee";

			reg = <0 0x010d3000 0 0x1000>;

			clocks = <&rpmhcc RPMH_HWKM_CLK>;

			clock-names = "core";

		};



		config_noc: interconnect@1500000 {

			compatible = "qcom,sm8350-config-noc";

			reg = <0 0x01500000 0 0xa580>;
@@ -1641,18 +1648,76 @@ 
			status = "disabled";

		};



		lpass_ag_noc: interconnect@3c40000 {

			compatible = "qcom,sm8350-lpass-ag-noc";

			reg = <0 0x03c40000 0 0xf080>;

			#interconnect-cells = <2>;

			qcom,bcm-voters = <&apps_bcm_voter>;

		ufs_mem_hc: ufshc@1d84000 {

			compatible = "qcom,sm8350-ufshc", "qcom,ufshc",

				     "jedec,ufs-2.0";

			reg = <0 0x01d84000 0 0x3000>;

			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

			phys = <&ufs_mem_phy_lanes>;

			phy-names = "ufsphy";

			lanes-per-direction = <2>;

			#reset-cells = <1>;

			resets = <&gcc GCC_UFS_PHY_BCR>;

			reset-names = "rst";



			power-domains = <&gcc UFS_PHY_GDSC>;



			iommus = <&apps_smmu 0xe0 0x0>;



			clock-names =

				"core_clk",

				"bus_aggr_clk",

				"iface_clk",

				"core_clk_unipro",

				"ref_clk",

				"tx_lane0_sync_clk",

				"rx_lane0_sync_clk",

				"rx_lane1_sync_clk";

			clocks =

				<&gcc GCC_UFS_PHY_AXI_CLK>,

				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

				<&gcc GCC_UFS_PHY_AHB_CLK>,

				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

				<&rpmhcc RPMH_CXO_CLK>,

				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

			freq-table-hz =

				<75000000 300000000>,

				<0 0>,

				<0 0>,

				<75000000 300000000>,

				<0 0>,

				<0 0>,

				<0 0>,

				<0 0>;

			status = "disabled";

		};



		compute_noc: interconnect@a0c0000 {

			compatible = "qcom,sm8350-compute-noc";

			reg = <0 0x0a0c0000 0 0xa180>;

			#interconnect-cells = <2>;

			qcom,bcm-voters = <&apps_bcm_voter>;

		ufs_mem_phy: phy@1d87000 {

			compatible = "qcom,sm8350-qmp-ufs-phy";

			reg = <0 0x01d87000 0 0x1c4>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			clock-names = "ref",

				      "ref_aux";

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;



			resets = <&ufs_mem_hc 0>;

			reset-names = "ufsphy";

			status = "disabled";



			ufs_mem_phy_lanes: phy@1d87400 {

				reg = <0 0x01d87400 0 0x188>,

				      <0 0x01d87600 0 0x200>,

				      <0 0x01d87c00 0 0x200>,

				      <0 0x01d87800 0 0x188>,

				      <0 0x01d87a00 0 0x200>;

				#clock-cells = <1>;

				#phy-cells = <0>;

			};

		};



		ipa: ipa@1e40000 {
@@ -1700,6 +1765,13 @@ 
			#hwlock-cells = <1>;

		};



		lpass_ag_noc: interconnect@3c40000 {

			compatible = "qcom,sm8350-lpass-ag-noc";

			reg = <0 0x03c40000 0 0xf080>;

			#interconnect-cells = <2>;

			qcom,bcm-voters = <&apps_bcm_voter>;

		};



		mpss: remoteproc@4080000 {

			compatible = "qcom,sm8350-mpss-pas";

			reg = <0x0 0x04080000 0x0 0x4040>;
@@ -1742,6 +1814,74 @@ 
			};

		};



		slpi: remoteproc@5c00000 {

			compatible = "qcom,sm8350-slpi-pas";

			reg = <0 0x05c00000 0 0x4000>;



			interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,

					      <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,

					      <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,

					      <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,

					      <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "wdog", "fatal", "ready",

					  "handover", "stop-ack";



			clocks = <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "xo";



			power-domains = <&rpmhpd SM8350_LCX>,

					<&rpmhpd SM8350_LMX>;

			power-domain-names = "lcx", "lmx";



			memory-region = <&pil_slpi_mem>;



			qcom,qmp = <&aoss_qmp>;



			qcom,smem-states = <&smp2p_slpi_out 0>;

			qcom,smem-state-names = "stop";



			status = "disabled";



			glink-edge {

				interrupts-extended = <&ipcc IPCC_CLIENT_SLPI

							     IPCC_MPROC_SIGNAL_GLINK_QMP

							     IRQ_TYPE_EDGE_RISING>;

				mboxes = <&ipcc IPCC_CLIENT_SLPI

						IPCC_MPROC_SIGNAL_GLINK_QMP>;



				label = "slpi";

				qcom,remote-pid = <3>;



				fastrpc {

					compatible = "qcom,fastrpc";

					qcom,glink-channels = "fastrpcglink-apps-dsp";

					label = "sdsp";

					qcom,non-secure-domain;

					#address-cells = <1>;

					#size-cells = <0>;



					compute-cb@1 {

						compatible = "qcom,fastrpc-compute-cb";

						reg = <1>;

						iommus = <&apps_smmu 0x0541 0x0>;

					};



					compute-cb@2 {

						compatible = "qcom,fastrpc-compute-cb";

						reg = <2>;

						iommus = <&apps_smmu 0x0542 0x0>;

					};



					compute-cb@3 {

						compatible = "qcom,fastrpc-compute-cb";

						reg = <3>;

						iommus = <&apps_smmu 0x0543 0x0>;

						/* note: shared-cb = <4> in downstream */

					};

				};

			};

		};



		pdc: interrupt-controller@b220000 {

			compatible = "qcom,sm8350-pdc", "qcom,pdc";

			reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
@@ -2012,153 +2152,6 @@ 
			};

		};



		rng: rng@10d3000 {

			compatible = "qcom,prng-ee";

			reg = <0 0x010d3000 0 0x1000>;

			clocks = <&rpmhcc RPMH_HWKM_CLK>;

			clock-names = "core";

		};



		ufs_mem_hc: ufshc@1d84000 {

			compatible = "qcom,sm8350-ufshc", "qcom,ufshc",

				     "jedec,ufs-2.0";

			reg = <0 0x01d84000 0 0x3000>;

			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

			phys = <&ufs_mem_phy_lanes>;

			phy-names = "ufsphy";

			lanes-per-direction = <2>;

			#reset-cells = <1>;

			resets = <&gcc GCC_UFS_PHY_BCR>;

			reset-names = "rst";



			power-domains = <&gcc UFS_PHY_GDSC>;



			iommus = <&apps_smmu 0xe0 0x0>;



			clock-names =

				"core_clk",

				"bus_aggr_clk",

				"iface_clk",

				"core_clk_unipro",

				"ref_clk",

				"tx_lane0_sync_clk",

				"rx_lane0_sync_clk",

				"rx_lane1_sync_clk";

			clocks =

				<&gcc GCC_UFS_PHY_AXI_CLK>,

				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

				<&gcc GCC_UFS_PHY_AHB_CLK>,

				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

				<&rpmhcc RPMH_CXO_CLK>,

				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

			freq-table-hz =

				<75000000 300000000>,

				<0 0>,

				<0 0>,

				<75000000 300000000>,

				<0 0>,

				<0 0>,

				<0 0>,

				<0 0>;

			status = "disabled";

		};



		ufs_mem_phy: phy@1d87000 {

			compatible = "qcom,sm8350-qmp-ufs-phy";

			reg = <0 0x01d87000 0 0x1c4>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			clock-names = "ref",

				      "ref_aux";

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;



			resets = <&ufs_mem_hc 0>;

			reset-names = "ufsphy";

			status = "disabled";



			ufs_mem_phy_lanes: phy@1d87400 {

				reg = <0 0x01d87400 0 0x188>,

				      <0 0x01d87600 0 0x200>,

				      <0 0x01d87c00 0 0x200>,

				      <0 0x01d87800 0 0x188>,

				      <0 0x01d87a00 0 0x200>;

				#clock-cells = <1>;

				#phy-cells = <0>;

			};

		};



		slpi: remoteproc@5c00000 {

			compatible = "qcom,sm8350-slpi-pas";

			reg = <0 0x05c00000 0 0x4000>;



			interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,

					      <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,

					      <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,

					      <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,

					      <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "wdog", "fatal", "ready",

					  "handover", "stop-ack";



			clocks = <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "xo";



			power-domains = <&rpmhpd SM8350_LCX>,

					<&rpmhpd SM8350_LMX>;

			power-domain-names = "lcx", "lmx";



			memory-region = <&pil_slpi_mem>;



			qcom,qmp = <&aoss_qmp>;



			qcom,smem-states = <&smp2p_slpi_out 0>;

			qcom,smem-state-names = "stop";



			status = "disabled";



			glink-edge {

				interrupts-extended = <&ipcc IPCC_CLIENT_SLPI

							     IPCC_MPROC_SIGNAL_GLINK_QMP

							     IRQ_TYPE_EDGE_RISING>;

				mboxes = <&ipcc IPCC_CLIENT_SLPI

						IPCC_MPROC_SIGNAL_GLINK_QMP>;



				label = "slpi";

				qcom,remote-pid = <3>;



				fastrpc {

					compatible = "qcom,fastrpc";

					qcom,glink-channels = "fastrpcglink-apps-dsp";

					label = "sdsp";

					qcom,non-secure-domain;

					#address-cells = <1>;

					#size-cells = <0>;



					compute-cb@1 {

						compatible = "qcom,fastrpc-compute-cb";

						reg = <1>;

						iommus = <&apps_smmu 0x0541 0x0>;

					};



					compute-cb@2 {

						compatible = "qcom,fastrpc-compute-cb";

						reg = <2>;

						iommus = <&apps_smmu 0x0542 0x0>;

					};



					compute-cb@3 {

						compatible = "qcom,fastrpc-compute-cb";

						reg = <3>;

						iommus = <&apps_smmu 0x0543 0x0>;

						/* note: shared-cb = <4> in downstream */

					};

				};

			};

		};



		sdhc_2: mmc@8804000 {

			compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";

			reg = <0 0x08804000 0 0x1000>;
@@ -2307,6 +2300,13 @@ 
			reg-names = "llcc_base", "llcc_broadcast_base";

		};



		compute_noc: interconnect@a0c0000 {

			compatible = "qcom,sm8350-compute-noc";

			reg = <0 0x0a0c0000 0 0xa180>;

			#interconnect-cells = <2>;

			qcom,bcm-voters = <&apps_bcm_voter>;

		};



		usb_1: usb@a6f8800 {

			compatible = "qcom,sm8350-dwc3", "qcom,dwc3";

			reg = <0 0x0a6f8800 0 0x400>;