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Commit 14016e4a authored by Conor Dooley's avatar Conor Dooley Committed by Claudiu Beznea
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clk: microchip: mpfs: add MSS pll's set & round rate



The MSS pll is not a fixed frequency clock, so add set() & round_rate()
support.
Control is limited to a 7 bit output divider as other devices on the
FPGA occupy the other three outputs of the PLL & prevent changing
the multiplier.

Reviewed-by: default avatarDaire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-9-conor.dooley@microchip.com
parent 356a5048
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