Commit 13e6b812 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
Browse files

MIPS: mm: Remove special handling for OCTEON CPUs 



Macro cpu_has_mips_r2_exec_hazard correctly handles OCTEON CPUs,
so we don't need the extra switch cases for them.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 5cad8323

arch/mips/mm/tlbex.c

+4 −20
Original line number Diff line number Diff line
@@ -2123,16 +2123,8 @@ static void build_r4000_tlb_load_handler(void) 


		uasm_i_tlbr(&p);



		switch (current_cpu_type()) {

		case CPU_CAVIUM_OCTEON:

		case CPU_CAVIUM_OCTEON_PLUS:

		case CPU_CAVIUM_OCTEON2:

			break;

		default:

		if (cpu_has_mips_r2_exec_hazard)

			uasm_i_ehb(&p);

			break;

		}



		/* Examine  entrylo 0 or 1 based on ptr. */

		if (use_bbit_insns()) {
@@ -2197,16 +2189,8 @@ static void build_r4000_tlb_load_handler(void) 


		uasm_i_tlbr(&p);



		switch (current_cpu_type()) {

		case CPU_CAVIUM_OCTEON:

		case CPU_CAVIUM_OCTEON_PLUS:

		case CPU_CAVIUM_OCTEON2:

			break;

		default:

		if (cpu_has_mips_r2_exec_hazard)

			uasm_i_ehb(&p);

			break;

		}



		/* Examine  entrylo 0 or 1 based on ptr. */

		if (use_bbit_insns()) {