Commit 13d45964 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'octeontx2-af-external-ptp-clock' 



Hariprasad Kelam says:

====================
Externel ptp clock support

Externel ptp support is required in a scenario like connecting
a external timing device to the chip for time synchronization.
This series of patches adds support to ptp driver to use external
clock and enables PTP config in CN10K MAC block (RPM). Currently
PTP configuration is left unchanged in FLR handler these patches
addresses the same.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
,
parents 128cfb88 99bbc4ae

drivers/net/ethernet/marvell/octeontx2/af/cgx.c

+5 −5
Original line number Diff line number Diff line
@@ -838,9 +838,6 @@ void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable) 
	if (!cgx)

		return;



	if (is_dev_rpm(cgx))

		return;



	if (enable) {

		/* Enable inbound PTP timestamping */

		cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
@@ -1545,9 +1542,11 @@ static int cgx_lmac_exit(struct cgx *cgx) 
static void cgx_populate_features(struct cgx *cgx)

{

	if (is_dev_rpm(cgx))

		cgx->hw_features =  (RVU_MAC_RPM | RVU_LMAC_FEAT_FC);

		cgx->hw_features = (RVU_LMAC_FEAT_DMACF | RVU_MAC_RPM |

				    RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP);

	else

		cgx->hw_features = (RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP);

		cgx->hw_features = (RVU_LMAC_FEAT_FC  | RVU_LMAC_FEAT_HIGIG2 |

				    RVU_LMAC_FEAT_PTP | RVU_LMAC_FEAT_DMACF);

}



static struct mac_ops	cgx_mac_ops    = {
@@ -1571,6 +1570,7 @@ static struct mac_ops cgx_mac_ops = { 
	.mac_get_pause_frm_status =	cgx_lmac_get_pause_frm_status,

	.mac_enadis_pause_frm =		cgx_lmac_enadis_pause_frm,

	.mac_pause_frm_config =		cgx_lmac_pause_frm_config,

	.mac_enadis_ptp_config =	cgx_lmac_ptp_config,

};



static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id)

drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h

+5 −0
Original line number Diff line number Diff line
@@ -102,6 +102,11 @@ struct mac_ops { 
	void			(*mac_pause_frm_config)(void  *cgxd,

							int lmac_id,

							bool enable);



	/* Enable/Disable Inbound PTP */

	void			(*mac_enadis_ptp_config)(void  *cgxd,

							 int lmac_id,

							 bool enable);

};



struct cgx {

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

+25 −19
Original line number Diff line number Diff line
@@ -154,23 +154,23 @@ M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 
M(CGX_PTP_RX_DISABLE,	0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp)	\

M(CGX_CFG_PAUSE_FRM,	0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg,	\

			       cgx_pause_frm_cfg)			\

M(CGX_FW_DATA_GET,	0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \

M(CGX_FEC_SET,		0x210, cgx_set_fec_param, fec_mode, fec_mode) \

M(CGX_FEC_STATS,	0x211, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \

M(CGX_GET_PHY_FEC_STATS, 0x212, cgx_get_phy_fec_stats, msg_req, msg_rsp) \

M(CGX_FW_DATA_GET,	0x213, cgx_get_aux_link_info, msg_req, cgx_fw_data) \

M(CGX_SET_LINK_MODE,	0x214, cgx_set_link_mode, cgx_set_link_mode_req,\

			       cgx_set_link_mode_rsp)	\

M(CGX_FEATURES_GET,	0x215, cgx_features_get, msg_req,		\

			       cgx_features_info_msg)			\

M(RPM_STATS,		0x216, rpm_stats, msg_req, rpm_stats_rsp)	\

M(CGX_MAC_ADDR_ADD,	0x217, cgx_mac_addr_add, cgx_mac_addr_add_req,    \

M(CGX_MAC_ADDR_ADD,	0x211, cgx_mac_addr_add, cgx_mac_addr_add_req,    \

				cgx_mac_addr_add_rsp)		\

M(CGX_MAC_ADDR_DEL,	0x218, cgx_mac_addr_del, cgx_mac_addr_del_req,    \

M(CGX_MAC_ADDR_DEL,	0x212, cgx_mac_addr_del, cgx_mac_addr_del_req,    \

			       msg_rsp)		\

M(CGX_MAC_MAX_ENTRIES_GET, 0x219, cgx_mac_max_entries_get, msg_req,    \

M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req,    \

				  cgx_max_dmac_entries_get_rsp)		\

M(CGX_MAC_ADDR_RESET,	0x21A, cgx_mac_addr_reset, msg_req, msg_rsp)	\

M(CGX_MAC_ADDR_UPDATE,	0x21B, cgx_mac_addr_update, cgx_mac_addr_update_req, \

M(CGX_FEC_STATS,	0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \

M(CGX_SET_LINK_MODE,	0x218, cgx_set_link_mode, cgx_set_link_mode_req,\

			       cgx_set_link_mode_rsp)	\

M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \

M(CGX_FEATURES_GET,	0x21B, cgx_features_get, msg_req,		\

			       cgx_features_info_msg)			\

M(RPM_STATS,		0x21C, rpm_stats, msg_req, rpm_stats_rsp)	\

M(CGX_MAC_ADDR_RESET,	0x21D, cgx_mac_addr_reset, msg_req, msg_rsp)	\

M(CGX_MAC_ADDR_UPDATE,	0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \

			       msg_rsp)					\

/* NPA mbox IDs (range 0x400 - 0x5FF) */				\

M(NPA_LF_ALLOC,		0x400, npa_lf_alloc,				\
@@ -583,10 +583,13 @@ struct cgx_mac_addr_update_req { 
};



#define RVU_LMAC_FEAT_FC		BIT_ULL(0) /* pause frames */

#define RVU_LMAC_FEAT_PTP		BIT_ULL(1) /* precision time protocol */

#define RVU_MAC_VERSION			BIT_ULL(2)

#define RVU_MAC_CGX			BIT_ULL(3)

#define RVU_MAC_RPM			BIT_ULL(4)

#define	RVU_LMAC_FEAT_HIGIG2		BIT_ULL(1)

			/* flow control from physical link higig2 messages */

#define RVU_LMAC_FEAT_PTP		BIT_ULL(2) /* precison time protocol */

#define RVU_LMAC_FEAT_DMACF		BIT_ULL(3) /* DMAC FILTER */

#define RVU_MAC_VERSION			BIT_ULL(4)

#define RVU_MAC_CGX			BIT_ULL(5)

#define RVU_MAC_RPM			BIT_ULL(6)



struct cgx_features_info_msg {

	struct mbox_msghdr hdr;
@@ -1417,12 +1420,15 @@ struct npc_mcam_get_stats_rsp { 
enum ptp_op {

	PTP_OP_ADJFINE = 0,

	PTP_OP_GET_CLOCK = 1,

	PTP_OP_GET_TSTMP = 2,

	PTP_OP_SET_THRESH = 3,

};



struct ptp_req {

	struct mbox_msghdr hdr;

	u8 op;

	s64 scaled_ppm;

	u64 thresh;

};



struct ptp_rsp {

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

+82 −51
Original line number Diff line number Diff line
@@ -27,54 +27,29 @@ 
#define PCI_DEVID_CN10K_PTP			0xA09E



#define PCI_PTP_BAR_NO				0

#define PCI_RST_BAR_NO				0



#define PTP_CLOCK_CFG				0xF00ULL

#define PTP_CLOCK_CFG_PTP_EN			BIT_ULL(0)

#define PTP_CLOCK_CFG_EXT_CLK_EN		BIT_ULL(1)

#define PTP_CLOCK_CFG_EXT_CLK_IN_MASK		GENMASK_ULL(7, 2)

#define PTP_CLOCK_CFG_TSTMP_EDGE		BIT_ULL(9)

#define PTP_CLOCK_CFG_TSTMP_EN			BIT_ULL(8)

#define PTP_CLOCK_CFG_TSTMP_IN_MASK		GENMASK_ULL(15, 10)

#define PTP_CLOCK_CFG_PPS_EN			BIT_ULL(30)

#define PTP_CLOCK_CFG_PPS_INV			BIT_ULL(31)



#define PTP_PPS_HI_INCR				0xF60ULL

#define PTP_PPS_LO_INCR				0xF68ULL

#define PTP_PPS_THRESH_HI			0xF58ULL



#define PTP_CLOCK_LO				0xF08ULL

#define PTP_CLOCK_HI				0xF10ULL

#define PTP_CLOCK_COMP				0xF18ULL



#define RST_BOOT				0x1600ULL

#define RST_MUL_BITS				GENMASK_ULL(38, 33)

#define CLOCK_BASE_RATE				50000000ULL

#define PTP_TIMESTAMP				0xF20ULL



static struct ptp *first_ptp_block;

static const struct pci_device_id ptp_id_table[];



static u64 get_clock_rate(void)

{

	u64 cfg, ret = CLOCK_BASE_RATE * 16;

	struct pci_dev *pdev;

	void __iomem *base;



	/* To get the input clock frequency with which PTP co-processor

	 * block is running the base frequency(50 MHz) needs to be multiplied

	 * with multiplier bits present in RST_BOOT register of RESET block.

	 * Hence below code gets the multiplier bits from the RESET PCI

	 * device present in the system.

	 */

	pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,

			      PCI_DEVID_OCTEONTX2_RST, NULL);

	if (!pdev)

		goto error;



	base = pci_ioremap_bar(pdev, PCI_RST_BAR_NO);

	if (!base)

		goto error_put_pdev;



	cfg = readq(base + RST_BOOT);

	ret = CLOCK_BASE_RATE * FIELD_GET(RST_MUL_BITS, cfg);



	iounmap(base);



error_put_pdev:

	pci_dev_put(pdev);



error:

	return ret;

}



struct ptp *ptp_get(void)

{

	struct ptp *ptp = first_ptp_block;
@@ -145,13 +120,74 @@ static int ptp_get_clock(struct ptp *ptp, u64 *clk) 
	return 0;

}



void ptp_start(struct ptp *ptp, u64 sclk, u32 ext_clk_freq, u32 extts)

{

	struct pci_dev *pdev;

	u64 clock_comp;

	u64 clock_cfg;



	if (!ptp)

		return;



	pdev = ptp->pdev;



	if (!sclk) {

		dev_err(&pdev->dev, "PTP input clock cannot be zero\n");

		return;

	}



	/* sclk is in MHz */

	ptp->clock_rate = sclk * 1000000;



	/* Enable PTP clock */

	clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG);



	if (ext_clk_freq) {

		ptp->clock_rate = ext_clk_freq;

		/* Set GPIO as PTP clock source */

		clock_cfg &= ~PTP_CLOCK_CFG_EXT_CLK_IN_MASK;

		clock_cfg |= PTP_CLOCK_CFG_EXT_CLK_EN;

	}



	if (extts) {

		clock_cfg |= PTP_CLOCK_CFG_TSTMP_EDGE;

		/* Set GPIO as timestamping source */

		clock_cfg &= ~PTP_CLOCK_CFG_TSTMP_IN_MASK;

		clock_cfg |= PTP_CLOCK_CFG_TSTMP_EN;

	}



	clock_cfg |= PTP_CLOCK_CFG_PTP_EN;

	clock_cfg |= PTP_CLOCK_CFG_PPS_EN | PTP_CLOCK_CFG_PPS_INV;

	writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);



	/* Set 50% duty cycle for 1Hz output */

	writeq(0x1dcd650000000000, ptp->reg_base + PTP_PPS_HI_INCR);

	writeq(0x1dcd650000000000, ptp->reg_base + PTP_PPS_LO_INCR);



	clock_comp = ((u64)1000000000ull << 32) / ptp->clock_rate;

	/* Initial compensation value to start the nanosecs counter */

	writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP);

}



static int ptp_get_tstmp(struct ptp *ptp, u64 *clk)

{

	*clk = readq(ptp->reg_base + PTP_TIMESTAMP);



	return 0;

}



static int ptp_set_thresh(struct ptp *ptp, u64 thresh)

{

	writeq(thresh, ptp->reg_base + PTP_PPS_THRESH_HI);



	return 0;

}



static int ptp_probe(struct pci_dev *pdev,

		     const struct pci_device_id *ent)

{

	struct device *dev = &pdev->dev;

	struct ptp *ptp;

	u64 clock_comp;

	u64 clock_cfg;

	int err;



	ptp = devm_kzalloc(dev, sizeof(*ptp), GFP_KERNEL);
@@ -172,17 +208,6 @@ static int ptp_probe(struct pci_dev *pdev, 


	ptp->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO];



	ptp->clock_rate = get_clock_rate();



	/* Enable PTP clock */

	clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG);

	clock_cfg |= PTP_CLOCK_CFG_PTP_EN;

	writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);



	clock_comp = ((u64)1000000000ull << 32) / ptp->clock_rate;

	/* Initial compensation value to start the nanosecs counter */

	writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP);



	pci_set_drvdata(pdev, ptp);

	if (!first_ptp_block)

		first_ptp_block = ptp;
@@ -272,6 +297,12 @@ int rvu_mbox_handler_ptp_op(struct rvu *rvu, struct ptp_req *req, 
	case PTP_OP_GET_CLOCK:

		err = ptp_get_clock(rvu->ptp, &rsp->clk);

		break;

	case PTP_OP_GET_TSTMP:

		err = ptp_get_tstmp(rvu->ptp, &rsp->clk);

		break;

	case PTP_OP_SET_THRESH:

		err = ptp_set_thresh(rvu->ptp, req->thresh);

		break;

	default:

		err = -EINVAL;

		break;

drivers/net/ethernet/marvell/octeontx2/af/ptp.h

+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ struct ptp { 


struct ptp *ptp_get(void);

void ptp_put(struct ptp *ptp);

void ptp_start(struct ptp *ptp, u64 sclk, u32 ext_clk_freq, u32 extts);



extern struct pci_driver ptp_driver;