Commit 13c2fde0 authored by Sandipan Das's avatar Sandipan Das Committed by Wenkuan Wang
Browse files

perf/x86/amd/uncore: Use rdmsr if rdpmc is unavailable 

mainline inclusion
from mainline-v6.7-rc1
commit 7ef0343855dc23a979a53b3143540f93f3e5bef8
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I9016O


CVE: NA

--------------------------------

Not all uncore PMUs may support the use of the RDPMC instruction for
reading counters. In such cases, read the count from the corresponding
PERF_CTR register using the RDMSR instruction.

Signed-off-by: default avatarSandipan Das <sandipan.das@amd.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/e9d994e32a3fcb39fa59fcf43ab4260d11aba097.1696425185.git.sandipan.das@amd.com
parent e3141096

arch/x86/events/amd/uncore.c

+13 −1
Original line number Diff line number Diff line
@@ -96,7 +96,16 @@ static void amd_uncore_read(struct perf_event *event) 
	 */



	prev = local64_read(&hwc->prev_count);



	/*

	 * Some uncore PMUs do not have RDPMC assignments. In such cases,

	 * read counts directly from the corresponding PERF_CTR.

	 */

	if (hwc->event_base_rdpmc < 0)

		rdmsrl(hwc->event_base, new);

	else

		rdpmcl(hwc->event_base_rdpmc, new);



	local64_set(&hwc->prev_count, new);

	delta = (new << COUNTER_SHIFT) - (prev << COUNTER_SHIFT);

	delta >>= COUNTER_SHIFT;
@@ -164,6 +173,9 @@ static int amd_uncore_add(struct perf_event *event, int flags) 
	hwc->event_base_rdpmc = pmu->rdpmc_base + hwc->idx;

	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;



	if (pmu->rdpmc_base < 0)

		hwc->event_base_rdpmc = -1;



	if (flags & PERF_EF_START)

		event->pmu->start(event, PERF_EF_RELOAD);