Commit 13a77336 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/cadence' 

- Convert cadence to use standard "dma-ranges" DT property instead of its
  own "cdns,no-bar-match-nbits" (Kishon Vijay Abraham I)

- Fix pm_runtime_put_sync() issues in cadence error paths (Kishon Vijay
  Abraham I)

- Add PTR_ALIGN_DOWN macro (Kishon Vijay Abraham I)

- Convert cadence r/w accessors to only 32-bit accesses (Kishon Vijay
  Abraham I)

- Add cadence support to start Link and check Link status (Kishon Vijay
  Abraham I)

- Allow custom PCI ops for cadence-based drivers (Kishon Vijay Abraham I)

- Remove "mem" from cadence reg binding since it's not memory and it
  overlaps the PCIe config and memory region (Kishon Vijay Abraham I)

- Add cadence ->cpu_addr_fixup() for platforms that require absolute
  addresses in the ATU, not just offsets (Kishon Vijay Abraham I)

- Update cadence Vendor IDs using local management registers, not
  architected config space (Kishon Vijay Abraham I)

- Add cadence endpoint driver MSI-X support (Kishon Vijay Abraham I)

- Add bindings and driver for TI J721E SoC, supporting both host and
  endpoint mode (Kishon Vijay Abraham I)

* remotes/lorenzo/pci/cadence:
  MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe
  misc: pci_endpoint_test: Add J721E in pci_device_id table
  PCI: j721e: Add TI J721E PCIe driver
  dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC
  dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC
  PCI: cadence: Add MSI-X support to Endpoint driver
  PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register
  PCI: cadence: Add new *ops* for CPU addr fixup
  dt-bindings: PCI: cadence: Remove "mem" from reg binding
  PCI: cadence: Allow pci_host_bridge to have custom pci_ops
  PCI: cadence: Add support to start link and verify link status
  PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses
  linux/kernel.h: Add PTR_ALIGN_DOWN macro
  PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path
  PCI: cadence: Use "dma-ranges" instead of "cdns,no-bar-match-nbits" property
parents 5b17dbab 0dbe77c9

Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml

+3 −5
Original line number Diff line number Diff line
@@ -18,13 +18,12 @@ properties: 
    const: cdns,cdns-pcie-host



  reg:

    maxItems: 3

    maxItems: 2



  reg-names:

    items:

      - const: reg

      - const: cfg

      - const: mem



  msi-parent: true
@@ -49,9 +48,8 @@ examples: 
            device-id = <0x0200>;



            reg = <0x0 0xfb000000  0x0 0x01000000>,

                  <0x0 0x41000000  0x0 0x00001000>,

                  <0x0 0x40000000  0x0 0x04000000>;

            reg-names = "reg", "cfg", "mem";

                  <0x0 0x41000000  0x0 0x00001000>;

            reg-names = "reg", "cfg";



            ranges = <0x02000000 0x0 0x42000000  0x0 0x42000000  0x0 0x1000000>,

                     <0x01000000 0x0 0x43000000  0x0 0x43000000  0x0 0x0010000>;

Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml

0 → 100644
+94 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/

%YAML 1.2

---

$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: TI J721E PCI EP (PCIe Wrapper)



maintainers:

  - Kishon Vijay Abraham I <kishon@ti.com>



allOf:

  - $ref: "cdns-pcie-ep.yaml#"



properties:

  compatible:

    enum:

      - ti,j721e-pcie-ep



  reg:

    maxItems: 4



  reg-names:

    items:

      - const: intd_cfg

      - const: user_cfg

      - const: reg

      - const: mem



  ti,syscon-pcie-ctrl:

    description: Phandle to the SYSCON entry required for configuring PCIe mode

                 and link speed.

    allOf:

      - $ref: /schemas/types.yaml#/definitions/phandle



  power-domains:

    maxItems: 1



  clocks:

    maxItems: 1

    description: clock-specifier to represent input to the PCIe



  clock-names:

    items:

      - const: fck



  dma-coherent:

    description: Indicates that the PCIe IP block can ensure the coherency



required:

  - compatible

  - reg

  - reg-names

  - ti,syscon-pcie-ctrl

  - max-link-speed

  - num-lanes

  - power-domains

  - clocks

  - clock-names

  - cdns,max-outbound-regions

  - dma-coherent

  - max-functions

  - phys

  - phy-names



examples:

  - |

    #include <dt-bindings/soc/ti,sci_pm_domain.h>



    bus {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie0_ep: pcie-ep@d000000 {

           compatible = "ti,j721e-pcie-ep";

           reg = <0x00 0x02900000 0x00 0x1000>,

                 <0x00 0x02907000 0x00 0x400>,

                 <0x00 0x0d000000 0x00 0x00800000>,

                 <0x00 0x10000000 0x00 0x08000000>;

           reg-names = "intd_cfg", "user_cfg", "reg", "mem";

           ti,syscon-pcie-ctrl = <&pcie0_ctrl>;

           max-link-speed = <3>;

           num-lanes = <2>;

           power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;

           clocks = <&k3_clks 239 1>;

           clock-names = "fck";

           cdns,max-outbound-regions = <16>;

           max-functions = /bits/ 8 <6>;

           dma-coherent;

           phys = <&serdes0_pcie_link>;

           phy-names = "pcie-phy";

       };

    };

Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml

0 → 100644
+113 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/

%YAML 1.2

---

$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: TI J721E PCI Host (PCIe Wrapper)



maintainers:

  - Kishon Vijay Abraham I <kishon@ti.com>



allOf:

  - $ref: "cdns-pcie-host.yaml#"



properties:

  compatible:

    enum:

      - ti,j721e-pcie-host



  reg:

    maxItems: 4



  reg-names:

    items:

      - const: intd_cfg

      - const: user_cfg

      - const: reg

      - const: cfg



  ti,syscon-pcie-ctrl:

    description: Phandle to the SYSCON entry required for configuring PCIe mode

      and link speed.

    allOf:

      - $ref: /schemas/types.yaml#/definitions/phandle



  power-domains:

    maxItems: 1



  clocks:

    maxItems: 1

    description: clock-specifier to represent input to the PCIe



  clock-names:

    items:

      - const: fck



  vendor-id:

    const: 0x104c



  device-id:

    const: 0xb00d



  msi-map: true



required:

  - compatible

  - reg

  - reg-names

  - ti,syscon-pcie-ctrl

  - max-link-speed

  - num-lanes

  - power-domains

  - clocks

  - clock-names

  - vendor-id

  - device-id

  - msi-map

  - dma-coherent

  - dma-ranges

  - ranges

  - reset-gpios

  - phys

  - phy-names



examples:

  - |

    #include <dt-bindings/soc/ti,sci_pm_domain.h>

    #include <dt-bindings/gpio/gpio.h>



    bus {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie0_rc: pcie@2900000 {

            compatible = "ti,j721e-pcie-host";

            reg = <0x00 0x02900000 0x00 0x1000>,

                  <0x00 0x02907000 0x00 0x400>,

                  <0x00 0x0d000000 0x00 0x00800000>,

                  <0x00 0x10000000 0x00 0x00001000>;

            reg-names = "intd_cfg", "user_cfg", "reg", "cfg";

            ti,syscon-pcie-ctrl = <&pcie0_ctrl>;

            max-link-speed = <3>;

            num-lanes = <2>;

            power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;

            clocks = <&k3_clks 239 1>;

            clock-names = "fck";

            device_type = "pci";

            #address-cells = <3>;

            #size-cells = <2>;

            bus-range = <0x0 0xf>;

            vendor-id = <0x104c>;

            device-id = <0xb00d>;

            msi-map = <0x0 &gic_its 0x0 0x10000>;

            dma-coherent;

            reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;

            phys = <&serdes0_pcie_link>;

            phy-names = "pcie-phy";

            ranges = <0x01000000 0x0 0x10001000  0x00 0x10001000  0x0 0x0010000>,

                     <0x02000000 0x0 0x10011000  0x00 0x10011000  0x0 0x7fef000>;

            dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;

        };

    };

MAINTAINERS

+3 −1
Original line number Diff line number Diff line
@@ -13149,12 +13149,14 @@ S: Maintained 
F:	Documentation/devicetree/bindings/pci/designware-pcie.txt

F:	drivers/pci/controller/dwc/*designware*









PCI DRIVER FOR TI DRA7XX









PCI DRIVER FOR TI DRA7XX/J721E









M:	Kishon Vijay Abraham I <kishon@ti.com>









L:	linux-omap@vger.kernel.org









L:	linux-pci@vger.kernel.org









L:	linux-arm-kernel@lists.infradead.org









S:	Supported









F:	Documentation/devicetree/bindings/pci/ti-pci.txt









F:	drivers/pci/controller/cadence/pci-j721e.c









F:	drivers/pci/controller/dwc/pci-dra7xx.c

















PCI DRIVER FOR TI KEYSTONE
































drivers/misc/pci_endpoint_test.c



+9
−0






























Original line number
Diff line number
Diff line







@@ -68,6 +68,7 @@







#define PCI_ENDPOINT_TEST_FLAGS			0x2c









#define FLAG_USE_DMA				BIT(0)



















#define PCI_DEVICE_ID_TI_J721E			0xb00d









#define PCI_DEVICE_ID_TI_AM654			0xb00c



















#define is_am654_pci_dev(pdev)		\








@@ -932,6 +933,11 @@ static const struct pci_endpoint_test_data am654_data = {







	.irq_type = IRQ_TYPE_MSI,









};



















static const struct pci_endpoint_test_data j721e_data = {









	.alignment = 256,









	.irq_type = IRQ_TYPE_MSI,









};



















static const struct pci_device_id pci_endpoint_test_tbl[] = {









	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x),









	  .driver_data = (kernel_ulong_t)&default_data,








@@ -946,6 +952,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {







	},









	{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),









	},









	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),









	  .driver_data = (kernel_ulong_t)&j721e_data,









	},









	{ }









};









MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);