Commit 1328953e authored by Tianyang Zhang's avatar Tianyang Zhang Committed by Hongchen Zhang
Browse files

LoongArch: Add AVEC irqchip support 

LoongArch inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IAZ3D3



--------------------------------

Introduce the advanced extended interrupt controllers (AVECINTC). This
feature will allow each core to have 256 independent interrupt vectors
and MSI interrupts can be independently routed to any vector on any CPU.

Co-developed-by: default avatarJianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: default avatarJianmin Lv <lvjianmin@loongson.cn>
Co-developed-by: default avatarLiupu Wang <wangliupu@loongson.cn>
Signed-off-by: default avatarLiupu Wang <wangliupu@loongson.cn>
Co-developed-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
Signed-off-by: default avatarTianyang Zhang <zhangtianyang@loongson.cn>
parent 43acbd37

Documentation/arch/loongarch/irq-chip-model.rst

+32 −0
Original line number Diff line number Diff line
@@ -85,6 +85,38 @@ to CPUINTC directly:: 
    | Devices |

    +---------+



Advanced Extended IRQ model

===========================



In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go

to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go

to AVECINTC, and then go to CPUINTC directly, while all other devices interrupts

go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::



 +-----+     +-----------------------+     +-------+

 | IPI | --> |        CPUINTC        | <-- | Timer |

 +-----+     +-----------------------+     +-------+

              ^          ^          ^

              |          |          |

       +---------+ +----------+ +---------+     +-------+

       | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |

       +---------+ +----------+ +---------+     +-------+

            ^            ^

            |            |

       +---------+  +---------+

       | PCH-PIC |  | PCH-MSI |

       +---------+  +---------+

         ^     ^           ^

         |     |           |

 +---------+ +---------+ +---------+

 | Devices | | PCH-LPC | | Devices |

 +---------+ +---------+ +---------+

                  ^

                  |

             +---------+

             | Devices |

             +---------+



ACPI-related definitions

========================

Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst

+32 −0
Original line number Diff line number Diff line
@@ -87,6 +87,38 @@ PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC:: 
    | Devices |

    +---------+



高级扩展IRQ模型

===============



在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，

CPU串口（UARTs）中断发送到LIOINTC，PCH-MSI中断发送到AVECINTC，而后通过AVECINTC直接

送达CPUINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/PCH-LPC，然后由EIOINTC

统一收集，再直接到达CPUINTC::



 +-----+     +-----------------------+     +-------+

 | IPI | --> |        CPUINTC        | <-- | Timer |

 +-----+     +-----------------------+     +-------+

              ^          ^          ^

              |          |          |

       +---------+ +----------+ +---------+     +-------+

       | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |

       +---------+ +----------+ +---------+     +-------+

            ^            ^

            |            |

       +---------+  +---------+

       | PCH-PIC |  | PCH-MSI |

       +---------+  +---------+

         ^     ^           ^

         |     |           |

 +---------+ +---------+ +---------+

 | Devices | | PCH-LPC | | Devices |

 +---------+ +---------+ +---------+

                  ^

                  |

             +---------+

             | Devices |

             +---------+



ACPI相关的定义

==============

MAINTAINERS

+1 −0
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@@ -12401,6 +12401,7 @@ F: Documentation/arch/loongarch/ 
F:	Documentation/translations/zh_CN/arch/loongarch/

F:	arch/loongarch/

F:	drivers/*/*loongarch*

F:	drivers/*/*loongson*









LOONGSON GPIO DRIVER









M:	Yinbo Zhu <zhuyinbo@loongson.cn>
































arch/loongarch/Kconfig



+1
−0






























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Diff line







@@ -77,6 +77,7 @@ config LOONGARCH







	select GENERIC_ENTRY









	select GENERIC_GETTIMEOFDAY









	select GENERIC_IOREMAP if !ARCH_IOREMAP









	select GENERIC_IRQ_MATRIX_ALLOCATOR









	select GENERIC_IRQ_MULTI_HANDLER









	select GENERIC_IRQ_PROBE









	select GENERIC_IRQ_SHOW
































arch/loongarch/include/asm/cpu-features.h



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−0






























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@@ -65,5 +65,6 @@







#define cpu_has_guestid		cpu_opt(LOONGARCH_CPU_GUESTID)









#define cpu_has_hypervisor	cpu_opt(LOONGARCH_CPU_HYPERVISOR)









#define cpu_has_ptw		cpu_opt(LOONGARCH_CPU_PTW)









#define cpu_has_avecint		cpu_opt(LOONGARCH_CPU_AVECINT)



















#endif /* __ASM_CPU_FEATURES_H */