Unverified Commit 13188fc5 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!4842 Intel-sig: intel_idle: add Sierra Forest SoC support on 5.10 

Merge Pull Request from: @jiayingbao 
 
Add Sierra Forest SoC C-states, which are C1, C1E, C6S, and C6SP.

Sierra Forest SoC is built with modules, each module includes 4 cores
(Crestmont microarchitecture). There is one L2 cache per module, shared
between the 4 cores.

There is no core C6 state, but there is C6S state, which has module scope:
when all 4 cores request C6S, the entire module (4 cores + L2 cache)
enters the low power state.

C6SP state has package scope - when all modules in the package enter C6S,
the package enters the power state mode.

upstream commit 92813fd5b1562e547120c8489137b040892fe1bc 
 
Link:https://gitee.com/openeuler/kernel/pulls/4842

 

Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Reviewed-by: default avatarAichun Shi <aichun.shi@intel.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 0161928e af8e11f2

drivers/idle/intel_idle.c

+44 −0
Original line number Diff line number Diff line
@@ -1063,6 +1063,43 @@ static struct cpuidle_state snr_cstates[] __initdata = { 
		.enter = NULL }

};



static struct cpuidle_state srf_cstates[] __initdata = {

	{

		.name = "C1",

		.desc = "MWAIT 0x00",

		.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_ALWAYS_ENABLE,

		.exit_latency = 1,

		.target_residency = 1,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.name = "C1E",

		.desc = "MWAIT 0x01",

		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,

		.exit_latency = 2,

		.target_residency = 10,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.name = "C6S",

		.desc = "MWAIT 0x22",

		.flags = MWAIT2flg(0x22) | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 270,

		.target_residency = 700,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.name = "C6SP",

		.desc = "MWAIT 0x23",

		.flags = MWAIT2flg(0x23) | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 310,

		.target_residency = 900,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.enter = NULL }

};



static const struct idle_cpu idle_cpu_nehalem __initconst = {

	.state_table = nehalem_cstates,

	.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
@@ -1196,6 +1233,12 @@ static const struct idle_cpu idle_cpu_snr __initconst = { 
	.use_acpi = true,

};



static const struct idle_cpu idle_cpu_srf __initconst = {

	.state_table = srf_cstates,

	.disable_promotion_to_c1e = true,

	.use_acpi = true,

};



static const struct x86_cpu_id intel_idle_ids[] __initconst = {

	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP,		&idle_cpu_nhx),

	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM,		&idle_cpu_nehalem),
@@ -1238,6 +1281,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS,	&idle_cpu_bxt),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D,	&idle_cpu_dnv),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	&idle_cpu_snr),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT_X,	&idle_cpu_srf),

	{}

};