Commit 12fc7b1a authored by Marijn Suijten's avatar Marijn Suijten Committed by Rob Clark
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drm/msm/dsi_phy_10nm: Replace parent names with clk_hw pointers 



parent_hw pointers are easier to manage and cheaper to use than
repeatedly formatting the parent name and subsequently leaving the clk
framework to perform lookups based on that name.

Signed-off-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/491923/
Link: https://lore.kernel.org/r/20220629225331.357308-11-marijn.suijten@somainline.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 9fcb9120

drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c

+36 −43
Original line number Diff line number Diff line
@@ -574,24 +574,24 @@ static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy) 
 */

static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **provided_clocks)

{

	char clk_name[32], parent[32], vco_name[32];

	char parent2[32], parent3[32], parent4[32];

	char clk_name[32];

	struct clk_init_data vco_init = {

		.parent_data = &(const struct clk_parent_data) {

			.fw_name = "ref",

		},

		.num_parents = 1,

		.name = vco_name,

		.name = clk_name,

		.flags = CLK_IGNORE_UNUSED,

		.ops = &clk_ops_dsi_pll_10nm_vco,

	};

	struct device *dev = &pll_10nm->phy->pdev->dev;

	struct clk_hw *hw;

	struct clk_hw *hw, *pll_out_div, *pll_bit, *pll_by_2_bit;

	struct clk_hw *pll_post_out_div, *pclk_mux;

	int ret;



	DBG("DSI%d", pll_10nm->phy->id);



	snprintf(vco_name, sizeof(vco_name), "dsi%dvco_clk", pll_10nm->phy->id);

	snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_10nm->phy->id);

	pll_10nm->clk_hw.init = &vco_init;



	ret = devm_clk_hw_register(dev, &pll_10nm->clk_hw);
@@ -599,36 +599,34 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov 
		return ret;



	snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", pll_10nm->phy->id);

	snprintf(parent, sizeof(parent), "dsi%dvco_clk", pll_10nm->phy->id);



	hw = devm_clk_hw_register_divider(dev, clk_name, parent,

			CLK_SET_RATE_PARENT, pll_10nm->phy->pll_base +

	pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name,

			&pll_10nm->clk_hw, CLK_SET_RATE_PARENT,

			pll_10nm->phy->pll_base +

				REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,

			0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

	if (IS_ERR(pll_out_div)) {

		ret = PTR_ERR(pll_out_div);

		goto fail;

	}



	snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", pll_10nm->phy->id);

	snprintf(parent, sizeof(parent), "dsi%d_pll_out_div_clk", pll_10nm->phy->id);



	/* BIT CLK: DIV_CTRL_3_0 */

	hw = devm_clk_hw_register_divider(dev, clk_name, parent,

			CLK_SET_RATE_PARENT,

	pll_bit = devm_clk_hw_register_divider_parent_hw(dev, clk_name,

			pll_out_div, CLK_SET_RATE_PARENT,

			pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,

			0, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

	if (IS_ERR(pll_bit)) {

		ret = PTR_ERR(pll_bit);

		goto fail;

	}



	snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", pll_10nm->phy->id);

	snprintf(parent, sizeof(parent), "dsi%d_pll_bit_clk", pll_10nm->phy->id);



	/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */

	hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,

					       CLK_SET_RATE_PARENT, 1, 8);

	hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name,

			pll_bit, CLK_SET_RATE_PARENT, 1, 8);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

		goto fail;
@@ -637,48 +635,43 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov 
	provided_clocks[DSI_BYTE_PLL_CLK] = hw;



	snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);

	snprintf(parent, sizeof(parent), "dsi%d_pll_bit_clk", pll_10nm->phy->id);



	hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,

					       0, 1, 2);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

	pll_by_2_bit = devm_clk_hw_register_fixed_factor_parent_hw(dev,

			clk_name, pll_bit, 0, 1, 2);

	if (IS_ERR(pll_by_2_bit)) {

		ret = PTR_ERR(pll_by_2_bit);

		goto fail;

	}



	snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id);

	snprintf(parent, sizeof(parent), "dsi%d_pll_out_div_clk", pll_10nm->phy->id);



	hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,

					       0, 1, 4);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

	pll_post_out_div = devm_clk_hw_register_fixed_factor_parent_hw(dev,

			clk_name, pll_out_div, 0, 1, 4);

	if (IS_ERR(pll_post_out_div)) {

		ret = PTR_ERR(pll_post_out_div);

		goto fail;

	}



	snprintf(clk_name, sizeof(clk_name), "dsi%d_pclk_mux", pll_10nm->phy->id);

	snprintf(parent, sizeof(parent), "dsi%d_pll_bit_clk", pll_10nm->phy->id);

	snprintf(parent2, sizeof(parent2), "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);

	snprintf(parent3, sizeof(parent3), "dsi%d_pll_out_div_clk", pll_10nm->phy->id);

	snprintf(parent4, sizeof(parent4), "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id);



	hw = devm_clk_hw_register_mux(dev, clk_name,

			((const char *[]){

				parent, parent2, parent3, parent4,



	pclk_mux = devm_clk_hw_register_mux_parent_hws(dev, clk_name,

			((const struct clk_hw *[]){

				pll_bit,

				pll_by_2_bit,

				pll_out_div,

				pll_post_out_div,

			}), 4, 0, pll_10nm->phy->base +

				REG_DSI_10nm_PHY_CMN_CLK_CFG1,

			0, 2, 0, NULL);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

				REG_DSI_10nm_PHY_CMN_CLK_CFG1, 0, 2, 0, NULL);

	if (IS_ERR(pclk_mux)) {

		ret = PTR_ERR(pclk_mux);

		goto fail;

	}



	snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_dsiclk", pll_10nm->phy->id);

	snprintf(parent, sizeof(parent), "dsi%d_pclk_mux", pll_10nm->phy->id);



	/* PIX CLK DIV : DIV_CTRL_7_4*/

	hw = devm_clk_hw_register_divider(dev, clk_name, parent, 0,

			pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,

	hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name, pclk_mux,

			0, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,

			4, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);