Commit 12cdf9d2 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Shawn Guo
Browse files

arm64: dts: imx8mm-var-som-symphony: Adjust ethernet pin configuration 



The Symphony board uses GPIO from expander as Ethernet PHY reset pin,
not the GPIO1_IO9.

Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 510ed674

arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts

+20 −0
Original line number Diff line number Diff line
@@ -181,6 +181,26 @@ 
	status = "disabled";

};



&pinctrl_fec1 {

	fsl,pins = <

		MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3

		MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3

		MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f

		MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f

		MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f

		MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f

		MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91

		MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91

		MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91

		MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91

		MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f

		MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91

		MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91

		MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f

		/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */

	>;

};



&iomuxc {

	pinctrl_captouch: captouchgrp {

		fsl,pins = <