Commit 12aeaaba authored by Leo Yan's avatar Leo Yan Committed by Arnaldo Carvalho de Melo
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perf c2c: Update documentation for store metric 'N/A' 



The 'N/A' metric is added for store operations, update documentation to
reflect changes in the report table.

Signed-off-by: default avatarLeo Yan <leo.yan@linaro.org>
Acked-by: default avatarJiri Olsa <jolsa@kernel.org>
Cc: Adam Li <adamli@amperemail.onmicrosoft.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ali Saidi <alisaidi@amazon.com>
Cc: Alyssa Ross <hi@alyssa.is>
Cc: German Gomez <german.gomez@arm.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Joe Mario <jmario@redhat.com>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Li Huafei <lihuafei1@huawei.com>
Cc: Like Xu <likexu@tencent.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220518055729.1869566-4-leo.yan@linaro.org


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 550b4d6f

tools/perf/Documentation/perf-c2c.txt

+5 −3
Original line number Diff line number Diff line
@@ -189,9 +189,10 @@ For each cacheline in the 1) list we display following data: 
  Total stores

  - sum of all store accesses



  Store Reference - L1Hit, L1Miss

  Store Reference - L1Hit, L1Miss, N/A

    L1Hit - store accesses that hit L1

    L1Miss - store accesses that missed L1

    N/A - store accesses with memory level is not available



  Core Load Hit - FB, L1, L2

  - count of load hits in FB (Fill Buffer), L1 and L2 cache
@@ -210,8 +211,9 @@ For each offset in the 2) list we display following data: 
  HITM - Rmt, Lcl

  - % of Remote/Local HITM accesses for given offset within cacheline



  Store Refs - L1 Hit, L1 Miss

  - % of store accesses that hit/missed L1 for given offset within cacheline

  Store Refs - L1 Hit, L1 Miss, N/A

  - % of store accesses that hit L1, missed L1 and N/A (no available) memory

    level for given offset within cacheline



  Data address - Offset

  - offset address