Commit 12a18bb7 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

dt-bindings: pinctrl: qcom: allow nine interrupts on SM6350 



Almost all Qualcomm SoC Top Level Mode Multiplexers come with only
summary interrupt.  SM6350 is different because downstream and upstream
DTS have nine of the interrupts.  Allow such variation.

Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221230135645.56401-7-krzysztof.kozlowski@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 45277153

Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml

+3 −1
Original line number Diff line number Diff line
@@ -19,7 +19,9 @@ properties: 
  reg:

    maxItems: 1



  interrupts: true

  interrupts:

    maxItems: 1



  interrupt-controller: true

  "#interrupt-cells": true

  gpio-controller: true

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml

+3 −1
Original line number Diff line number Diff line
@@ -20,7 +20,9 @@ properties: 
  reg:

    maxItems: 1



  interrupts: true

  interrupts:

    maxItems: 1



  interrupt-controller: true

  "#interrupt-cells": true

  gpio-controller: true

Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml

+3 −1
Original line number Diff line number Diff line
@@ -22,7 +22,9 @@ properties: 
  reg:

    maxItems: 1



  interrupts: true

  interrupts:

    maxItems: 1



  interrupt-controller: true

  "#interrupt-cells": true

  gpio-controller: true

Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml

+3 −1
Original line number Diff line number Diff line
@@ -20,7 +20,9 @@ properties: 
  reg:

    maxItems: 1



  interrupts: true

  interrupts:

    maxItems: 1



  interrupt-controller: true

  '#interrupt-cells': true

  gpio-controller: true

Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml

+3 −1
Original line number Diff line number Diff line
@@ -20,7 +20,9 @@ properties: 
    description: Specifies the base address and size of the TLMM register space

    maxItems: 1



  interrupts: true

  interrupts:

    maxItems: 1



  interrupt-controller: true

  "#interrupt-cells": true

  gpio-controller: true