Merge tag 'for_3.7-rc3-fixes-pm' of... (126c414a) · Commits · EulixOS / Software / Kernel

arch/arm/mach-omap2/board-omap3beagle.c

+13 −9

Original line number	Diff line number	Diff line
		@@ -24,6 +24,7 @@
		#include <linux/input.h>
		#include <linux/gpio_keys.h>
		#include <linux/opp.h>
		#include <linux/cpu.h>

		#include <linux/mtd/mtd.h>
		#include <linux/mtd/partitions.h>
		@@ -444,27 +445,31 @@ static struct omap_board_mux board_mux[] __initdata = {
		};
		#endif

		static void __init beagle_opp_init(void)
		static int __init beagle_opp_init(void)
		{
		int r = 0;

		/* Initialize the omap3 opp table */
		if (omap3_opp_init()) {
		if (!machine_is_omap3_beagle())
		return 0;

		/* Initialize the omap3 opp table if not already created. */
		r = omap3_opp_init();
		if (IS_ERR_VALUE(r) && (r != -EEXIST)) {
		pr_err("%s: opp default init failed\n", __func__);
		return;
		return r;
		}

		/* Custom OPP enabled for all xM versions */
		if (cpu_is_omap3630()) {
		struct device mpu_dev, iva_dev;

		mpu_dev = omap_device_get_by_hwmod_name("mpu");
		mpu_dev = get_cpu_device(0);
		iva_dev = omap_device_get_by_hwmod_name("iva");

		if (IS_ERR(mpu_dev) \|\| IS_ERR(iva_dev)) {
		pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
		__func__, mpu_dev, iva_dev);
		return;
		return -ENODEV;
		}
		/* Enable MPU 1GHz and lower opps */
		r = opp_enable(mpu_dev, 800000000);
		@@ -484,8 +489,9 @@ static void __init beagle_opp_init(void)
		opp_disable(iva_dev, 660000000);
		}
		}
		return;
		return 0;
		}
		device_initcall(beagle_opp_init);

		static void __init omap3_beagle_init(void)
		{
		@@ -522,8 +528,6 @@ static void __init omap3_beagle_init(void)
		/* Ensure SDRC pins are mux'd for self-refresh */
		omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
		omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);

		beagle_opp_init();
		}

		MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")

arch/arm/mach-omap2/pm.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -91,6 +91,7 @@ extern void omap3_save_scratchpad_contents(void);

		#define PM_RTA_ERRATUM_i608 (1 << 0)
		#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
		#define PM_PER_MEMORIES_ERRATUM_i582 (1 << 2)

		#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
		extern u16 pm34xx_errata;

arch/arm/mach-omap2/pm34xx.c

+28 −2

Original line number	Diff line number	Diff line
		@@ -652,14 +652,17 @@ static void __init pm_errata_configure(void)
		/* Enable the l2 cache toggling in sleep logic */
		enable_omap3630_toggle_l2_on_restore();
		if (omap_rev() < OMAP3630_REV_ES1_2)
		pm34xx_errata \|= PM_SDRC_WAKEUP_ERRATUM_i583;
		pm34xx_errata \|= (PM_SDRC_WAKEUP_ERRATUM_i583 \|
		PM_PER_MEMORIES_ERRATUM_i582);
		} else if (cpu_is_omap34xx()) {
		pm34xx_errata \|= PM_PER_MEMORIES_ERRATUM_i582;
		}
		}

		int __init omap3_pm_init(void)
		{
		struct power_state pwrst, tmp;
		struct clockdomain neon_clkdm, mpu_clkdm;
		struct clockdomain neon_clkdm, mpu_clkdm, per_clkdm, wkup_clkdm;
		int ret;

		if (!omap3_has_io_chain_ctrl())
		@@ -711,6 +714,8 @@ int __init omap3_pm_init(void)

		neon_clkdm = clkdm_lookup("neon_clkdm");
		mpu_clkdm = clkdm_lookup("mpu_clkdm");
		per_clkdm = clkdm_lookup("per_clkdm");
		wkup_clkdm = clkdm_lookup("wkup_clkdm");

		#ifdef CONFIG_SUSPEND
		omap_pm_suspend = omap3_pm_suspend;
		@@ -727,6 +732,27 @@ int __init omap3_pm_init(void)
		if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
		omap3630_ctrl_disable_rta();

		/*
		* The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
		* not correctly reset when the PER powerdomain comes back
		* from OFF or OSWR when the CORE powerdomain is kept active.
		* See OMAP36xx Erratum i582 "PER Domain reset issue after
		* Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
		* complete workaround. The kernel must also prevent the PER
		* powerdomain from going to OSWR/OFF while the CORE
		* powerdomain is not going to OSWR/OFF. And if PER last
		* power state was off while CORE last power state was ON, the
		* UART3/4 and McBSP2/3 SIDETONE devices need to run a
		* self-test using their loopback tests; if that fails, those
		* devices are unusable until the PER/CORE can complete a transition
		* from ON to OSWR/OFF and then back to ON.
		*
		* XXX Technically this workaround is only needed if off-mode
		* or OSWR is enabled.
		*/
		if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
		clkdm_add_wkdep(per_clkdm, wkup_clkdm);

		clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
		if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
		omap3_secure_ram_storage =

arch/arm/mach-omap2/serial.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -329,6 +329,11 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,

		oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);

		if (console_uart_id == bdata->id) {
		omap_device_enable(pdev);
		pm_runtime_set_active(&pdev->dev);
		}

		oh->dev_attr = uart;

		if (((cpu_is_omap34xx() \|\| cpu_is_omap44xx()) && bdata->pads)