Commit 1267d983 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Marc Zyngier
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dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC 



Renesas RZ/Five (R9A07G043) SoC is equipped with NCEPLIC100 RISC-V
platform level interrupt controller from Andes Technology. NCEPLIC100
ignores subsequent EDGE interrupts until the previous EDGE interrupt is
completed, due to this issue we have to follow different interrupt flow
for EDGE and LEVEL interrupts.

This patch documents Renesas RZ/Five (R9A07G043) SoC.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220630100241.35233-2-samuel@sholland.org
parent a111daf0

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

+59 −5
Original line number Diff line number Diff line
@@ -26,9 +26,14 @@ description: 
  with priority below this threshold will not cause the PLIC to raise its

  interrupt line leading to the context.



  While the PLIC supports both edge-triggered and level-triggered interrupts,

  interrupt handlers are oblivious to this distinction and therefore it is not

  specified in the PLIC device-tree binding.

  The PLIC supports both edge-triggered and level-triggered interrupts. For

  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges

  seen while an interrupt handler is active; the PLIC may either queue them or

  ignore them. In the first case, handlers are oblivious to the trigger type, so

  it is not included in the interrupt specifier. In the second case, software

  needs to know the trigger type, so it can reorder the interrupt flow to avoid

  missing interrupts. This special handling is needed by at least the Renesas

  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100).



  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the

  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
@@ -47,6 +52,10 @@ maintainers: 
properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - renesas,r9a07g043-plic

          - const: andestech,nceplic100

      - items:

          - enum:

              - sifive,fu540-c000-plic
@@ -64,8 +73,7 @@ properties: 
  '#address-cells':

    const: 0



  '#interrupt-cells':

    const: 1

  '#interrupt-cells': true



  interrupt-controller: true
@@ -82,6 +90,12 @@ properties: 
    description:

      Specifies how many external interrupts are supported by this controller.



  clocks: true



  power-domains: true



  resets: true



required:

  - compatible

  - '#address-cells'
@@ -91,6 +105,46 @@ required: 
  - interrupts-extended

  - riscv,ndev



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - andestech,nceplic100



    then:

      properties:

        '#interrupt-cells':

          const: 2



    else:

      properties:

        '#interrupt-cells':

          const: 1



  - if:

      properties:

        compatible:

          contains:

            const: renesas,r9a07g043-plic



    then:

      properties:

        clocks:

          maxItems: 1



        power-domains:

          maxItems: 1



        resets:

          maxItems: 1



      required:

        - clocks

        - power-domains

        - resets



additionalProperties: false



examples: