Commit 123db17d authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-5.18-2022-02-11-1' of... 

Merge tag 'amd-drm-next-5.18-2022-02-11-1' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-5.18-2022-02-11-1:

amdgpu:
- Clean up of power management code
- Enable freesync video mode by default
- Clean up of RAS code
- Improve VRAM access for debug using SDMA
- Coding style cleanups
- SR-IOV fixes
- More display FP reorg
- TLB flush fixes for Arcuturus, Vega20
- Misc display fixes
- Rework special register access methods for SR-IOV
- DP2 fixes
- DP tunneling fixes
- DSC fixes
- More IP discovery cleanups
- Misc RAS fixes
- Enable both SMU i2c buses where applicable
- s2idle improvements
- DPCS header cleanup
- Add new CAP firmware support for SR-IOV

amdkfd:
- Misc cleanups
- SVM fixes
- CRIU support
- Clean up MQD manager

UAPI:
- Add interface to amdgpu CTX ioctl to request a stable power state for profiling
  https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/207
- Add amdkfd support for CRIU
  https://github.com/checkpoint-restore/criu/pull/1709
- Remove old unused amdkfd debugger interface
  Was only implemented for Kaveri and was only ever used by an old HSA tool that was never open sourced

radeon:
- Fix error handling in radeon_driver_open_kms
- UVD suspend fix
- Misc fixes

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220211220706.5803-1-alexander.deucher@amd.com
parents e7a09cea 7f161df1

drivers/gpu/drm/amd/amdgpu/aldebaran.c

+1 −1
Original line number Diff line number Diff line
@@ -260,7 +260,7 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) 
	adev->gfx.rlc.funcs->resume(adev);



	/* Wait for FW reset event complete */

	r = smu_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0);

	r = amdgpu_dpm_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0);

	if (r) {

		dev_err(adev->dev,

			"Failed to get response from firmware after reset\n");

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+26 −11
Original line number Diff line number Diff line
@@ -99,7 +99,6 @@ 
#include "amdgpu_gem.h"

#include "amdgpu_doorbell.h"

#include "amdgpu_amdkfd.h"

#include "amdgpu_smu.h"

#include "amdgpu_discovery.h"

#include "amdgpu_mes.h"

#include "amdgpu_umc.h"
@@ -109,6 +108,7 @@ 
#include "amdgpu_smuio.h"

#include "amdgpu_fdinfo.h"

#include "amdgpu_mca.h"

#include "amdgpu_ras.h"



#define MAX_GPU_INSTANCE		16
@@ -197,7 +197,6 @@ extern int amdgpu_emu_mode; 
extern uint amdgpu_smu_memory_pool_size;

extern int amdgpu_smu_pptable_id;

extern uint amdgpu_dc_feature_mask;

extern uint amdgpu_freesync_vid_mode;

extern uint amdgpu_dc_debug_mask;

extern uint amdgpu_dm_abm_level;

extern int amdgpu_backlight;
@@ -373,7 +372,8 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 
 */

bool amdgpu_get_bios(struct amdgpu_device *adev);

bool amdgpu_read_bios(struct amdgpu_device *adev);



bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,

				     u8 *bios, u32 length_bytes);

/*

 * Clocks

 */
@@ -950,12 +950,6 @@ struct amdgpu_device { 


	/* powerplay */

	struct amd_powerplay		powerplay;

	bool				pp_force_state_enabled;



	/* smu */

	struct smu_context		smu;



	/* dpm */

	struct amdgpu_pm		pm;

	u32				cg_flags;

	u32				pg_flags;
@@ -1100,6 +1094,8 @@ struct amdgpu_device { 
	uint32_t                        ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];



	bool				ram_is_direct_mapped;



	struct list_head                ras_list;

};



static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
@@ -1321,6 +1317,10 @@ void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 
		struct amdgpu_ring *ring);



void amdgpu_device_halt(struct amdgpu_device *adev);

u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,

				u32 reg);

void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,

				u32 reg, u32 v);



/* atpx handler */

#if defined(CONFIG_VGA_SWITCHEROO)
@@ -1408,12 +1408,10 @@ int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_sta 
int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);



void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);

bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);

void amdgpu_acpi_detect(void);

#else

static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }

static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }

static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }

static inline void amdgpu_acpi_detect(void) { }

static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }

static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
@@ -1422,6 +1420,14 @@ static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 
						 enum amdgpu_ss ss_state) { return 0; }

#endif



#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)

bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);

bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);

#else

static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }

static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }

#endif



int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,

			   uint64_t addr, struct amdgpu_bo **bo,

			   struct amdgpu_bo_va_mapping **mapping);
@@ -1452,6 +1458,15 @@ int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 
int amdgpu_device_set_pg_state(struct amdgpu_device *adev,

			       enum amd_powergating_state state);



static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)

{

	return amdgpu_gpu_recovery != 0 &&

		adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&

		adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&

		adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&

		adev->video_timeout != MAX_SCHEDULE_TIMEOUT;

}



#include "amdgpu_object.h"



static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

+32 −5
Original line number Diff line number Diff line
@@ -1031,6 +1031,20 @@ void amdgpu_acpi_detect(void) 
	}

}



#if IS_ENABLED(CONFIG_SUSPEND)

/**

 * amdgpu_acpi_is_s3_active

 *

 * @adev: amdgpu_device_pointer

 *

 * returns true if supported, false if not.

 */

bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev)

{

	return !(adev->flags & AMD_IS_APU) ||

		(pm_suspend_target_state == PM_SUSPEND_MEM);

}



/**

 * amdgpu_acpi_is_s0ix_active

 *
@@ -1040,11 +1054,24 @@ void amdgpu_acpi_detect(void) 
 */

bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev)

{

#if IS_ENABLED(CONFIG_AMD_PMC) && IS_ENABLED(CONFIG_SUSPEND)

	if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) {

		if (adev->flags & AMD_IS_APU)

			return pm_suspend_target_state == PM_SUSPEND_TO_IDLE;

	if (!(adev->flags & AMD_IS_APU) ||

	    (pm_suspend_target_state != PM_SUSPEND_TO_IDLE))

		return false;



	if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {

		dev_warn_once(adev->dev,

			      "Power consumption will be higher as BIOS has not been configured for suspend-to-idle.\n"

			      "To use suspend-to-idle change the sleep mode in BIOS setup.\n");

		return false;

	}

#endif



#if !IS_ENABLED(CONFIG_AMD_PMC)

	dev_warn_once(adev->dev,

		      "Power consumption will be higher as the kernel has not been compiled with CONFIG_AMD_PMC.\n");

	return false;

#else

	return true;

#endif /* CONFIG_AMD_PMC */

}



#endif /* CONFIG_SUSPEND */

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h

+6 −1
Original line number Diff line number Diff line
@@ -131,6 +131,7 @@ struct amdkfd_process_info { 
	atomic_t evicted_bos;

	struct delayed_work restore_userptr_work;

	struct pid *pid;

	bool block_mmu_notifications;

};



int amdgpu_amdkfd_init(void);
@@ -268,7 +269,7 @@ uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv); 
int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(

		struct amdgpu_device *adev, uint64_t va, uint64_t size,

		void *drm_priv, struct kgd_mem **mem,

		uint64_t *offset, uint32_t flags);

		uint64_t *offset, uint32_t flags, bool criu_resume);

int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(

		struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,

		uint64_t *size);
@@ -297,6 +298,10 @@ int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, 
				struct tile_config *config);

void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,

				bool reset);

bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem);

void amdgpu_amdkfd_block_mmu_notifications(void *p);

int amdgpu_amdkfd_criu_resume(void *p);



#if IS_ENABLED(CONFIG_HSA_AMD)

void amdgpu_amdkfd_gpuvm_init_mem_limits(void);

void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

+0 −3
Original line number Diff line number Diff line
@@ -37,10 +37,7 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = { 
	.hqd_sdma_is_occupied = kgd_arcturus_hqd_sdma_is_occupied,

	.hqd_destroy = kgd_gfx_v9_hqd_destroy,

	.hqd_sdma_destroy = kgd_arcturus_hqd_sdma_destroy,

	.address_watch_disable = kgd_gfx_v9_address_watch_disable,

	.address_watch_execute = kgd_gfx_v9_address_watch_execute,

	.wave_control_execute = kgd_gfx_v9_wave_control_execute,

	.address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,

	.get_atc_vmid_pasid_mapping_info =

				kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,

	.set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,