Commit 12320274 authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher
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drm/amd/display: Add feature flags to disable LTTPR



[Why]
Allow for disabling non transparent mode of LTTPR for running tests.

[How]
Add a feature flag and set them during init sequence. The flags are
already being used in DC.

Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 655ff353
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+7 −0
Original line number Diff line number Diff line
@@ -1453,6 +1453,13 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
	if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
		init_data.flags.edp_no_power_sequencing = true;

#ifdef CONFIG_DRM_AMD_DC_DCN
	if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
		init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
	if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
		init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
#endif

	init_data.flags.power_down_display_on_boot = true;

	if (check_seamless_boot_capability(adev)) {
+2 −0
Original line number Diff line number Diff line
@@ -231,6 +231,8 @@ enum DC_FEATURE_MASK {
	DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2), //0x4, disabled by default
	DC_PSR_MASK = (1 << 3), //0x8, disabled by default for dcn < 3.1
	DC_EDP_NO_POWER_SEQUENCING = (1 << 4), //0x10, disabled by default
	DC_DISABLE_LTTPR_DP1_4A = (1 << 5), //0x20, disabled by default
	DC_DISABLE_LTTPR_DP2_0 = (1 << 6), //0x40, disabled by default
};

enum DC_DEBUG_MASK {