Commit 11e78c39 authored by Huazhong Tan's avatar Huazhong Tan Committed by Zheng Zengkai
Browse files

net: hns3: add support for 1us unit GL configuration 

mainline inclusion
from mainline-v5.11-rc1
commit 5ac84b02
category: feature
bugzilla: 173966
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5ac84b02d372ff45bce48c78beedbffe7c9158c0



----------------------------------------------------------------------

For device whose version is above V3(include V3), the GL
configuration can set as 1us unit, so adds support for
configuring this field.

Signed-off-by: default avatarHuazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
Reviewed-by: default avatarli yongxin <liyongxin1@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 64b9f616

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+22 −4
Original line number Diff line number Diff line
@@ -224,17 +224,27 @@ void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 
void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,

				    u32 gl_value)

{

	u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);

	u32 new_val;



	writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);

	if (tqp_vector->rx_group.coal.unit_1us)

		new_val = gl_value | HNS3_INT_GL_1US;

	else

		new_val = hns3_gl_usec_to_reg(gl_value);



	writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);

}



void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,

				    u32 gl_value)

{

	u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);

	u32 new_val;



	if (tqp_vector->tx_group.coal.unit_1us)

		new_val = gl_value | HNS3_INT_GL_1US;

	else

		new_val = hns3_gl_usec_to_reg(gl_value);



	writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);

	writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);

}



void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
@@ -272,6 +282,14 @@ static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector, 
	rx_coal->flow_level = HNS3_FLOW_LOW;

	tx_coal->flow_level = HNS3_FLOW_LOW;



	/* device version above V3(include V3), GL can configure 1us

	 * unit, so uses 1us unit.

	 */

	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {

		tx_coal->unit_1us = 1;

		rx_coal->unit_1us = 1;

	}



	if (ae_dev->dev_specs.int_ql_max) {

		tx_coal->ql_enable = 1;

		rx_coal->ql_enable = 1;

drivers/net/ethernet/hisilicon/hns3/hns3_enet.h

+3 −0
Original line number Diff line number Diff line
@@ -427,6 +427,8 @@ enum hns3_flow_level_range { 
#define HNS3_INT_GL_18K			0x0036

#define HNS3_INT_GL_8K			0x007C



#define HNS3_INT_GL_1US			BIT(31)



#define HNS3_INT_RL_MAX			0x00EC

#define HNS3_INT_RL_ENABLE_MASK		0x40
@@ -438,6 +440,7 @@ struct hns3_enet_coalesce { 
	u16 int_ql_max;

	u8 gl_adapt_enable:1;

	u8 ql_enable:1;

	u8 unit_1us:1;

	enum hns3_flow_level_range flow_level;

};

drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c

+6 −0
Original line number Diff line number Diff line
@@ -1150,6 +1150,12 @@ static int hns3_check_gl_coalesce_para(struct net_device *netdev, 
		return -EINVAL;

	}



	/* device version above V3(include V3), GL uses 1us unit,

	 * so the round down is not needed.

	 */

	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)

		return 0;



	rx_gl = hns3_gl_round_down(cmd->rx_coalesce_usecs);

	if (rx_gl != cmd->rx_coalesce_usecs) {

		netdev_info(netdev,