Commit 11c70529 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull ARM SoC driver updates from Arnd Bergmann:
 "As usual, there are lots of minor driver changes across SoC platforms
  from NXP, Amlogic, AMD Zynq, Mediatek, Qualcomm, Apple and Samsung.
  These usually add support for additional chip variations in existing
  drivers, but also add features or bugfixes.

  The SCMI firmware subsystem gains a unified raw userspace interface
  through debugfs, which can be used for validation purposes.

  Newly added drivers include:

   - New power management drivers for StarFive JH7110, Allwinner D1 and
     Renesas RZ/V2M

   - A driver for Qualcomm battery and power supply status

   - A SoC device driver for identifying Nuvoton WPCM450 chips

   - A regulator coupler driver for Mediatek MT81xxv"

* tag 'soc-drivers-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (165 commits)
  power: supply: Introduce Qualcomm PMIC GLINK power supply
  soc: apple: rtkit: Do not copy the reg state structure to the stack
  soc: sunxi: SUN20I_PPU should depend on PM
  memory: renesas-rpc-if: Remove redundant division of dummy
  soc: qcom: socinfo: Add IDs for IPQ5332 and its variant
  dt-bindings: arm: qcom,ids: Add IDs for IPQ5332 and its variant
  dt-bindings: power: qcom,rpmpd: add RPMH_REGULATOR_LEVEL_LOW_SVS_L1
  firmware: qcom_scm: Move qcom_scm.h to include/linux/firmware/qcom/
  MAINTAINERS: Update qcom CPR maintainer entry
  dt-bindings: firmware: document Qualcomm SM8550 SCM
  dt-bindings: firmware: qcom,scm: add qcom,scm-sa8775p compatible
  soc: qcom: socinfo: Add Soc IDs for IPQ8064 and variants
  dt-bindings: arm: qcom,ids: Add Soc IDs for IPQ8064 and variants
  soc: qcom: socinfo: Add support for new field in revision 17
  soc: qcom: smd-rpm: Add IPQ9574 compatible
  soc: qcom: pmic_glink: remove redundant calculation of svid
  soc: qcom: stats: Populate all subsystem debugfs files
  dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes
  soc: qcom: pmic_glink: add CONFIG_NET/CONFIG_OF dependencies
  soc: qcom: pmic_glink: Introduce altmode support
  ...
parents d40b2f4c 524af30c
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What:           /sys/kernel/debug/dcc/.../ready
Date:           December 2022
Contact:        Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Description:
		This file is used to check the status of the dcc
		hardware if it's ready to receive user configurations.
		A 'Y' here indicates dcc is ready.

What:           /sys/kernel/debug/dcc/.../trigger
Date:           December 2022
Contact:        Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Description:
		This is the debugfs interface for manual software
		triggers. The trigger can be invoked by writing '1'
		to the file.

What:           /sys/kernel/debug/dcc/.../config_reset
Date:           December 2022
Contact:        Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Description:
		This file is used to reset the configuration of
		a dcc driver to the default configuration. When '1'
		is written to the file, all the previous addresses
		stored in the driver gets removed and users need to
		reconfigure addresses again.

What:           /sys/kernel/debug/dcc/.../[list-number]/config
Date:		 December 2022
Contact:        Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Description:
		This stores the addresses of the registers which
		can be read in case of a hardware crash or manual
		software triggers. The input addresses type
		can be one of following dcc instructions: read,
		write, read-write, and loop type. The lists need to
		be configured sequentially and not in a overlapping
		manner; e.g. users can jump to list x only after
		list y is configured and enabled. The input format for
		each type is as follows:

	        i) Read instruction

		   ::

		     echo R <addr> <n> <bus> >/sys/kernel/debug/dcc/../[list-number]/config

		   where:

		   <addr>
			The address to be read.

		   <n>
			The addresses word count, starting from address <1>.
			Each word is 32 bits (4 bytes). If omitted, defaulted
			to 1.

		   <bus type>
			The bus type, which can be either 'apb' or 'ahb'.
			The default is 'ahb' if leaved out.

		ii) Write instruction

		    ::

		      echo W <addr> <n> <bus type> > /sys/kernel/debug/dcc/../[list-number]/config

		    where:

		    <addr>
			The address to be written.

		    <n>
			The value to be written at <addr>.

		    <bus type>
			The bus type, which can be either 'apb' or 'ahb'.

	        iii) Read-write instruction

		     ::

		       echo RW <addr> <n> <mask> > /sys/kernel/debug/dcc/../[list-number]/config

		     where:

		     <addr>
			The address to be read and written.

		     <n>
		        The value to be written at <addr>.

		     <mask>
			The value mask.

		iv) Loop instruction

		    ::

		      echo L <loop count> <address count> <address>... > /sys/kernel/debug/dcc/../[list-number]/config

		    where:

		    <loop count>
			Number of iterations

		    <address count>
			total number of addresses to be written

		    <address>
			Space-separated list of addresses.

What:           /sys/kernel/debug/dcc/.../[list-number]/enable
Date:           December 2022
Contact:        Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Description:
		This debugfs interface is used for enabling the
		the dcc hardware. A file named "enable" is in the
		directory list number where users can enable/disable
		the specific list by writing boolean (1 or 0) to the
		file.

		On enabling the dcc, all the addresses specified
		by the user for the corresponding list is written
		into dcc sram which is read by the dcc hardware
		on manual or crash induced triggers. Lists must
		be configured and enabled sequentially, e.g. list
		2 can only be enabled when list 1 have so.
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What:		/sys/kernel/debug/scmi/<n>/instance_name
Date:		March 2023
KernelVersion:	6.3
Contact:	cristian.marussi@arm.com
Description:	The name of the underlying SCMI instance <n> described by
		all the debugfs accessors rooted at /sys/kernel/debug/scmi/<n>,
		expressed as the full name of the top DT SCMI node under which
		this SCMI instance is rooted.
Users:		Debugging, any userspace test suite

What:		/sys/kernel/debug/scmi/<n>/atomic_threshold_us
Date:		March 2023
KernelVersion:	6.3
Contact:	cristian.marussi@arm.com
Description:	An optional time value, expressed in microseconds, representing,
		on this SCMI instance <n>, the threshold above which any SCMI
		command, advertised to have an higher-than-threshold execution
		latency, should not be considered for atomic mode of operation,
		even if requested.
Users:		Debugging, any userspace test suite

What:		/sys/kernel/debug/scmi/<n>/transport/type
Date:		March 2023
KernelVersion:	6.3
Contact:	cristian.marussi@arm.com
Description:	A string representing the type of transport configured for this
		SCMI instance <n>.
Users:		Debugging, any userspace test suite

What:		/sys/kernel/debug/scmi/<n>/transport/is_atomic
Date:		March 2023
KernelVersion:	6.3
Contact:	cristian.marussi@arm.com
Description:	A boolean stating if the transport configured on the underlying
		SCMI instance <n> is capable of atomic mode of operation.
Users:		Debugging, any userspace test suite

What:		/sys/kernel/debug/scmi/<n>/transport/max_rx_timeout_ms
Date:		March 2023
KernelVersion:	6.3
Contact:	cristian.marussi@arm.com
Description:	Timeout in milliseconds allowed for SCMI synchronous replies
		for the currently configured SCMI transport for instance <n>.
Users:		Debugging, any userspace test suite

What:		/sys/kernel/debug/scmi/<n>/transport/max_msg_size
Date:		March 2023
KernelVersion:	6.3
Contact:	cristian.marussi@arm.com
Description:	Max message size of allowed SCMI messages for the currently
		configured SCMI transport for instance <n>.
Users:		Debugging, any userspace test suite

What:		/sys/kernel/debug/scmi/<n>/transport/tx_max_msg
Date:		March 2023
KernelVersion:	6.3
Contact:	cristian.marussi@arm.com
Description:	Max number of concurrently allowed in-flight SCMI messages for
		the currently configured SCMI transport for instance <n> on the
		TX channels.
Users:		Debugging, any userspace test suite

What:		/sys/kernel/debug/scmi/<n>/transport/rx_max_msg
Date:		March 2023
KernelVersion:	6.3
Contact:	cristian.marussi@arm.com
Description:	Max number of concurrently allowed in-flight SCMI messages for
		the currently configured SCMI transport for instance <n> on the
		RX channels.
Users:		Debugging, any userspace test suite
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What:		/sys/kernel/debug/scmi/<n>/raw/message
Date:		March 2023
KernelVersion:	6.3
Contact:	cristian.marussi@arm.com
Description:	SCMI Raw synchronous message injection/snooping facility; write
		a complete SCMI synchronous command message (header included)
		in little-endian binary format to have it sent to the configured
		backend SCMI server for instance <n>.
		Any subsequently received response can be read from this same
		entry if it arrived within the configured timeout.
		Each write to the entry causes one command request to be built
		and sent while the replies are read back one message at time
		(receiving an EOF at each message boundary).
Users:		Debugging, any userspace test suite

What:		/sys/kernel/debug/scmi/<n>/raw/message_async
Date:		March 2023
KernelVersion:	6.3
Contact:	cristian.marussi@arm.com
Description:	SCMI Raw asynchronous message injection/snooping facility; write
		a complete SCMI asynchronous command message (header included)
		in little-endian binary format to have it sent to the configured
		backend SCMI server for instance <n>.
		Any subsequently received response can be read from this same
		entry if it arrived within the configured timeout.
		Any additional delayed response received afterwards can be read
		from this same entry too if it arrived within the configured
		timeout.
		Each write to the entry causes one command request to be built
		and sent while the replies are read back one message at time
		(receiving an EOF at each message boundary).
Users:		Debugging, any userspace test suite

What:		/sys/kernel/debug/scmi/<n>/raw/errors
Date:		March 2023
KernelVersion:	6.3
Contact:	cristian.marussi@arm.com
Description:	SCMI Raw message errors facility; any kind of timed-out or
		generally unexpectedly received SCMI message, for instance <n>,
		can be read from this entry.
		Each read gives back one message at time (receiving an EOF at
		each message boundary).
Users:		Debugging, any userspace test suite

What:		/sys/kernel/debug/scmi/<n>/raw/notification
Date:		March 2023
KernelVersion:	6.3
Contact:	cristian.marussi@arm.com
Description:	SCMI Raw notification snooping facility; any notification
		emitted by the backend SCMI server, for instance <n>, can be
		read from this entry.
		Each read gives back one message at time (receiving an EOF at
		each message boundary).
Users:		Debugging, any userspace test suite

What:		/sys/kernel/debug/scmi/<n>/raw/reset
Date:		March 2023
KernelVersion:	6.3
Contact:	cristian.marussi@arm.com
Description:	SCMI Raw stack reset facility; writing a value to this entry
		causes the internal queues of any kind of received message,
		still pending to be read out for instance <n>, to be immediately
		flushed.
		Can be used to reset and clean the SCMI Raw stack between to
		different test-run.
Users:		Debugging, any userspace test suite

What:		/sys/kernel/debug/scmi/<n>/raw/channels/<m>/message
Date:		March 2023
KernelVersion:	6.3
Contact:	cristian.marussi@arm.com
Description:	SCMI Raw synchronous message injection/snooping facility; write
		a complete SCMI synchronous command message (header included)
		in little-endian binary format to have it sent to the configured
		backend SCMI server for instance <n> through the <m> transport
		channel.
		Any subsequently received response can be read from this same
		entry if it arrived on channel <m> within the configured
		timeout.
		Each write to the entry causes one command request to be built
		and sent while the replies are read back one message at time
		(receiving an EOF at each message boundary).
		Channel identifier <m> matches the SCMI protocol number which
		has been associated with this transport channel in the DT
		description, with base protocol number 0x10 being the default
		channel for this instance.
		Note that these per-channel entries rooted at <..>/channels
		exist only if the transport is configured to have more than
		one default channel.
Users:		Debugging, any userspace test suite

What:		/sys/kernel/debug/scmi/<n>/raw/channels/<m>/message_async
Date:		March 2023
KernelVersion:	6.3
Contact:	cristian.marussi@arm.com
Description:	SCMI Raw asynchronous message injection/snooping facility; write
		a complete SCMI asynchronous command message (header included)
		in little-endian binary format to have it sent to the configured
		backend SCMI server for instance <n> through the <m> transport
		channel.
		Any subsequently received response can be read from this same
		entry if it arrived on channel <m> within the configured
		timeout.
		Any additional delayed response received afterwards can be read
		from this same entry too if it arrived within the configured
		timeout.
		Each write to the entry causes one command request to be built
		and sent while the replies are read back one message at time
		(receiving an EOF at each message boundary).
		Channel identifier <m> matches the SCMI protocol number which
		has been associated with this transport channel in the DT
		description, with base protocol number 0x10 being the default
		channel for this instance.
		Note that these per-channel entries rooted at <..>/channels
		exist only if the transport is configured to have more than
		one default channel.
Users:		Debugging, any userspace test suite
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@@ -31,7 +31,11 @@ properties:
              - mediatek,mt8173-mmsys
              - mediatek,mt8183-mmsys
              - mediatek,mt8186-mmsys
              - mediatek,mt8188-vdosys0
              - mediatek,mt8192-mmsys
              - mediatek,mt8195-vdosys1
              - mediatek,mt8195-vppsys0
              - mediatek,mt8195-vppsys1
              - mediatek,mt8365-mmsys
          - const: syscon

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/firmware/amlogic,meson-gxbb-sm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amlogic Secure Monitor (SM)

description:
  In the Amlogic SoCs the Secure Monitor code is used to provide access to the
  NVMEM, enable JTAG, set USB boot, etc...

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

properties:
  compatible:
    oneOf:
      - const: amlogic,meson-gxbb-sm
      - items:
          - const: amlogic,meson-gx-sm
          - const: amlogic,meson-gxbb-sm

  power-controller:
    type: object
    $ref: /schemas/power/amlogic,meson-sec-pwrc.yaml#

required:
  - compatible

additionalProperties: false

examples:
  - |
    firmware {
        secure-monitor {
            compatible = "amlogic,meson-gxbb-sm";
        };
    };
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