Commit 11af4c37 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm64: PMU: Implement PMUv3p5 long counter support 



PMUv3p5 (which is mandatory with ARMv8.5) comes with some extra
features:

- All counters are 64bit

- The overflow point is controlled by the PMCR_EL0.LP bit

Add the required checks in the helpers that control counter
width and overflow, as well as the sysreg handling for the LP
bit. A new kvm_pmu_is_3p5() helper makes it easy to spot the
PMUv3p5 specific handling.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20221113163832.3154370-14-maz@kernel.org
parent d82e0dfd

arch/arm64/kvm/pmu-emul.c

+5 −3
Original line number Diff line number Diff line
@@ -52,13 +52,15 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm) 
 */

static bool kvm_pmu_idx_is_64bit(struct kvm_vcpu *vcpu, u64 select_idx)

{

	return (select_idx == ARMV8_PMU_CYCLE_IDX);

	return (select_idx == ARMV8_PMU_CYCLE_IDX || kvm_pmu_is_3p5(vcpu));

}



static bool kvm_pmu_idx_has_64bit_overflow(struct kvm_vcpu *vcpu, u64 select_idx)

{

	return (select_idx == ARMV8_PMU_CYCLE_IDX &&

		__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_LC);

	u64 val = __vcpu_sys_reg(vcpu, PMCR_EL0);



	return (select_idx < ARMV8_PMU_CYCLE_IDX && (val & ARMV8_PMU_PMCR_LP)) ||

	       (select_idx == ARMV8_PMU_CYCLE_IDX && (val & ARMV8_PMU_PMCR_LC));

}



static bool kvm_pmu_counter_can_chain(struct kvm_vcpu *vcpu, u64 idx)

arch/arm64/kvm/sys_regs.c

+4 −0
Original line number Diff line number Diff line
@@ -654,6 +654,8 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 
	       | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);

	if (!kvm_supports_32bit_el0())

		val |= ARMV8_PMU_PMCR_LC;

	if (!kvm_pmu_is_3p5(vcpu))

		val &= ~ARMV8_PMU_PMCR_LP;

	__vcpu_sys_reg(vcpu, r->reg) = val;

}
@@ -703,6 +705,8 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
		val |= p->regval & ARMV8_PMU_PMCR_MASK;

		if (!kvm_supports_32bit_el0())

			val |= ARMV8_PMU_PMCR_LC;

		if (!kvm_pmu_is_3p5(vcpu))

			val &= ~ARMV8_PMU_PMCR_LP;

		__vcpu_sys_reg(vcpu, PMCR_EL0) = val;

		kvm_pmu_handle_pmcr(vcpu, val);

		kvm_vcpu_pmu_restore_guest(vcpu);

include/kvm/arm_pmu.h

+7 −0
Original line number Diff line number Diff line
@@ -89,6 +89,12 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); 
			vcpu->arch.pmu.events = *kvm_get_pmu_events();	\

	} while (0)



/*

 * Evaluates as true when emulating PMUv3p5, and false otherwise.

 */

#define kvm_pmu_is_3p5(vcpu)						\

	(vcpu->kvm->arch.dfr0_pmuver.imp >= ID_AA64DFR0_EL1_PMUVer_V3P5)



u8 kvm_arm_pmu_get_pmuver_limit(void);



#else
@@ -153,6 +159,7 @@ static inline u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1) 
}



#define kvm_vcpu_has_pmu(vcpu)		({ false; })

#define kvm_pmu_is_3p5(vcpu)		({ false; })

static inline void kvm_pmu_update_vcpu_events(struct kvm_vcpu *vcpu) {}

static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {}

static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {}