Commit 11a89708 authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915/tc: Add/use helpers to retrieve TypeC port properties 



Instead of directly accessing the TypeC port internal struct members,
add/use helpers to retrieve the corresponding properties.

No functional change.

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210921002313.1132357-6-imre.deak@intel.com
parent 30e114ef

drivers/gpu/drm/i915/display/intel_ddi.c

+11 −20
Original line number Diff line number Diff line
@@ -288,7 +288,7 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 


	if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {

		intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);

		if (dig_port->tc_mode != TC_PORT_TBT_ALT)

		if (!intel_tc_port_in_tbt_alt_mode(dig_port))

			intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;

	}

}
@@ -885,8 +885,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 


	dig_port = enc_to_dig_port(encoder);



	if (!intel_phy_is_tc(dev_priv, phy) ||

	    dig_port->tc_mode != TC_PORT_TBT_ALT) {

	if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {

		drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);

		dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,

								   dig_port->ddi_io_power_domain);
@@ -1180,7 +1179,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 
	int n_entries, ln;

	u32 val;



	if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)

	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))

		return;



	ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
@@ -1317,7 +1316,7 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 
	u32 val, dpcnt_mask, dpcnt_val;

	int n_entries, ln;



	if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)

	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))

		return;



	ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
@@ -2084,7 +2083,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 
	u8 width;



	if (!intel_phy_is_tc(dev_priv, phy) ||

	    dig_port->tc_mode == TC_PORT_TBT_ALT)

	    intel_tc_port_in_tbt_alt_mode(dig_port))

		return;



	if (DISPLAY_VER(dev_priv) >= 12) {
@@ -2109,7 +2108,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 
	switch (pin_assignment) {

	case 0x0:

		drm_WARN_ON(&dev_priv->drm,

			    dig_port->tc_mode != TC_PORT_LEGACY);

			    !intel_tc_port_in_legacy_mode(dig_port));

		if (width == 1) {

			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;

		} else {
@@ -2354,7 +2353,6 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, 
{

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);

	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);

	int level = intel_ddi_dp_level(intel_dp, crtc_state);
@@ -2378,8 +2376,7 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, 
	intel_ddi_enable_clock(encoder, crtc_state);



	/* 4. Enable IO power */

	if (!intel_phy_is_tc(dev_priv, phy) ||

	    dig_port->tc_mode != TC_PORT_TBT_ALT)

	if (!intel_tc_port_in_tbt_alt_mode(dig_port))

		dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,

								   dig_port->ddi_io_power_domain);
@@ -2468,7 +2465,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 
{

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);

	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);

	int level = intel_ddi_dp_level(intel_dp, crtc_state);
@@ -2505,8 +2501,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 
	intel_ddi_enable_clock(encoder, crtc_state);



	/* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */

	if (!intel_phy_is_tc(dev_priv, phy) ||

	    dig_port->tc_mode != TC_PORT_TBT_ALT) {

	if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {

		drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);

		dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,

								   dig_port->ddi_io_power_domain);
@@ -2611,7 +2606,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum port port = encoder->port;

	enum phy phy = intel_port_to_phy(dev_priv, port);

	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);

	int level = intel_ddi_dp_level(intel_dp, crtc_state);
@@ -2630,8 +2624,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 


	intel_ddi_enable_clock(encoder, crtc_state);



	if (!intel_phy_is_tc(dev_priv, phy) ||

	    dig_port->tc_mode != TC_PORT_TBT_ALT) {

	if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {

		drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);

		dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,

								   dig_port->ddi_io_power_domain);
@@ -2801,7 +2794,6 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 
	struct intel_dp *intel_dp = &dig_port->dp;

	bool is_mst = intel_crtc_has_type(old_crtc_state,

					  INTEL_OUTPUT_DP_MST);

	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);



	if (!is_mst)

		intel_dp_set_infoframes(encoder, false,
@@ -2844,8 +2836,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 
	intel_pps_vdd_on(intel_dp);

	intel_pps_off(intel_dp);



	if (!intel_phy_is_tc(dev_priv, phy) ||

	    dig_port->tc_mode != TC_PORT_TBT_ALT)

	if (!intel_tc_port_in_tbt_alt_mode(dig_port))

		intel_display_power_put(dev_priv,

					dig_port->ddi_io_power_domain,

					fetch_and_zero(&dig_port->ddi_io_wakeref));
@@ -3320,7 +3311,7 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 
						intel_ddi_main_link_aux_domain(dig_port));

	}



	if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)

	if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))

		/*

		 * Program the lane count for static/dynamic connections on

		 * Type-C ports.  Skip this step for TBT.

drivers/gpu/drm/i915/display/intel_display.c

+1 −5
Original line number Diff line number Diff line
@@ -3494,11 +3494,7 @@ enum intel_display_power_domain intel_port_to_power_domain(enum port port) 
enum intel_display_power_domain

intel_aux_power_domain(struct intel_digital_port *dig_port)

{

	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);

	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);



	if (intel_phy_is_tc(dev_priv, phy) &&

	    dig_port->tc_mode == TC_PORT_TBT_ALT) {

	if (intel_tc_port_in_tbt_alt_mode(dig_port)) {

		switch (dig_port->aux_ch) {

		case AUX_CH_C:

			return POWER_DOMAIN_AUX_C_TBT;

drivers/gpu/drm/i915/display/intel_display_power.c

+2 −2
Original line number Diff line number Diff line
@@ -560,7 +560,7 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, 
	if (drm_WARN_ON(&dev_priv->drm, !dig_port))

		return;



	if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port)

	if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port))

		return;



	drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
@@ -629,7 +629,7 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, 
	 * exit sequence.

	 */

	timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port);

	if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port)

	if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port))

		icl_tc_cold_exit(dev_priv);



	hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected);

drivers/gpu/drm/i915/display/intel_dp_aux.c

+1 −5
Original line number Diff line number Diff line
@@ -150,9 +150,6 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, 
				u32 unused)

{

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	struct drm_i915_private *i915 =

			to_i915(dig_port->base.base.dev);

	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);

	u32 ret;



	/*
@@ -170,8 +167,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, 
	      DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |

	      DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);



	if (intel_phy_is_tc(i915, phy) &&

	    dig_port->tc_mode == TC_PORT_TBT_ALT)

	if (intel_tc_port_in_tbt_alt_mode(dig_port))

		ret |= DP_AUX_CH_CTL_TBT_IO;



	return ret;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+3 −2
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include "intel_dpio_phy.h"

#include "intel_dpll.h"

#include "intel_dpll_mgr.h"

#include "intel_tc.h"



/**

 * DOC: Display PLLs
@@ -3101,8 +3102,8 @@ static void icl_update_active_dpll(struct intel_atomic_state *state, 
		enc_to_dig_port(encoder);



	if (primary_port &&

	    (primary_port->tc_mode == TC_PORT_DP_ALT ||

	     primary_port->tc_mode == TC_PORT_LEGACY))

	    (intel_tc_port_in_dp_alt_mode(primary_port) ||

	     intel_tc_port_in_legacy_mode(primary_port)))

		port_dpll_id = ICL_PORT_DPLL_MG_PHY;



	icl_set_active_port_dpll(crtc_state, port_dpll_id);