Commit 116de80a authored by Michal Simek's avatar Michal Simek
Browse files

arm64: zynqmp: Setup clock for DP and DPDMA 



Clocks are coming from shared HW design where these frequencies should be
aligned with PLL setup.

Signed-off-by: default avatarMichal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/807e22371394222f728ff7d6b190a96a12145439.1683034376.git.michal.simek@amd.com
parent fc57b6c9

arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -248,10 +248,14 @@ 


&zynqmp_dpdma {

	clocks = <&zynqmp_clk DPDMA_REF>;

	assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */

};



&zynqmp_dpsub {

	clocks = <&zynqmp_clk TOPSW_LSBUS>,

		 <&zynqmp_clk DP_AUDIO_REF>,

		 <&zynqmp_clk DP_VIDEO_REF>;

	assigned-clocks = <&zynqmp_clk DP_STC_REF>,

			  <&zynqmp_clk DP_AUDIO_REF>,

			  <&zynqmp_clk DP_VIDEO_REF>;  /* rpll, rpll, vpll */

};

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso

+2 −0
Original line number Diff line number Diff line
@@ -98,10 +98,12 @@ 
	status = "disabled";

	phy-names = "dp-phy0", "dp-phy1";

	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;

	assigned-clock-rates = <27000000>, <25000000>, <300000000>;

};



&zynqmp_dpdma {

	status = "okay";

	assigned-clock-rates = <600000000>;

};



&usb0 {

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso

+2 −0
Original line number Diff line number Diff line
@@ -79,10 +79,12 @@ 
	status = "disabled";

	phy-names = "dp-phy0", "dp-phy1";

	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;

	assigned-clock-rates = <27000000>, <25000000>, <300000000>;

};



&zynqmp_dpdma {

	status = "okay";

	assigned-clock-rates = <600000000>;

};



&usb0 {