Commit 1151e3cd authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mmc-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc 

Pull MMC updates from Ulf Hansson:
 "MMC core:
   - Use common polling loop for CMD1
   - Add support for DT compatibles for card quirks and use it for ti,wl1251
   - Fixup storing of the OCR mask for MMC_QUIRK_NONSTD_SDIO

  MMC host:
   - dw_mmc: Add support for MMC_GEN_CMDs
   - dw_mmc: Fixup calculation of the data timeout
   - dw_mmc-exynos: Add support for the ARTPEC-8 variant
   - jz4740: Add support for bi-directional DMA channels
   - mmci: Add support for eMMC HS200 mode for the stm32 sdmmc variant
   - mmci: Add support for stm32 sdmmc variant revision v2.2
   - mtk-sd: A couple of various minor improvements
   - omap_hsmmc: Drop redundant initialization for the ti,wl1251 chip
   - sdhci-esdhc-imx: Add support for the i.MXRT series variant
   - sdhci-esdhc-imx: Add Haibo Chen as maintainer
   - sdhci-pci: Add support for the Intel ADL variant
   - sdhci-pci-gli: GL975[50]: Add support for the Apple ARM64 variant
   - sdhci-pci-o2micro: Improve support for SDR104/HS200"

* tag 'mmc-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (54 commits)
  dt-bindings: mmc: synopsys-dw-mshc: integrate Altera and Imagination
  mmc: pwrseq: Use bitmap_free() to free bitmap
  dt-bindings: mmc: PL18x stop relying on order of dma-names
  dt-bindings: mmc: sdhci-msm: Add compatible string for msm8994
  mmc: au1xmmc: propagate errors from platform_get_irq()
  mmc: sdhci-pci-o2micro: Restore the SD clock's base clock frequency
  mmc: sdhci-pci-o2micro: Improve card input timing at SDR104/HS200 mode
  mmc: mtk-sd: Assign src_clk parent to src_clk_cg for legacy DTs
  mmc: mtk-sd: Fix usage of devm_clk_get_optional()
  mmc: mtk-sd: Take action for no-sdio device-tree parameter
  mmc: mtk-sd: Use BIT() and GENMASK() macros to describe fields
  mmc: mtk-sd: Use readl_poll_timeout instead of open-coded polling
  MAINTAINERS: Add i.MX sdhci maintainer
  mmc: jz4740: Support using a bi-directional DMA channel
  dt-bindings: mmc: ingenic: Support using bi-directional DMA channel
  mmc: dw_mmc: Do not wait for DTO in case of error
  mmc: dw_mmc: Add driver callbacks for data read timeout
  mmc: dw_mmc-exynos: Add support for ARTPEC-8
  dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8
  mmc: meson-mx-sdio: add IRQ check
  ...
parents 1cc8d14c 356f3f2c

Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml

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Original line number Diff line number Diff line
@@ -118,6 +118,9 @@ properties: 
  phy-names:

    const: phy_arasan



  resets:

    maxItems: 1



  arasan,soc-ctl-syscon:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

Documentation/devicetree/bindings/mmc/arm,pl18x.yaml

+18 −1
Original line number Diff line number Diff line
@@ -53,6 +53,12 @@ properties: 
        items:

          - const: arm,pl18x

          - const: arm,primecell

      - description: Entry for STMicroelectronics variant of PL18x.

          This dedicated compatible is used by bootloaders.

        items:

          - const: st,stm32-sdmmc2

          - const: arm,pl18x

          - const: arm,primecell



  clocks:

    description: One or two clocks, the "apb_pclk" and the "MCLK"
@@ -60,6 +66,18 @@ properties: 
    minItems: 1

    maxItems: 2



  dmas:

    maxItems: 2



  dma-names:

    oneOf:

      - items:

          - const: tx

          - const: rx

      - items:

          - const: rx

          - const: tx



  power-domains: true



  resets:
@@ -213,7 +231,6 @@ examples: 
      arm,primecell-periphid = <0x10153180>;

      reg = <0x52007000 0x1000>;

      interrupts = <49>;

      interrupt-names = "cmd_irq";

      clocks = <&rcc 0>;

      clock-names = "apb_pclk";

      resets = <&rcc 1>;

Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt

deleted100644 → 0
+0 −53
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* BROADCOM BRCMSTB/BMIPS SDHCI Controller



This file documents differences between the core properties in mmc.txt

and the properties used by the sdhci-brcmstb driver.



NOTE: The driver disables all UHS speed modes by default and depends

on Device Tree properties to enable them for SoC/Board combinations

that support them.



Required properties:

- compatible: should be one of the following

  - "brcm,bcm7425-sdhci"

  - "brcm,bcm7445-sdhci"

  - "brcm,bcm7216-sdhci"



Refer to clocks/clock-bindings.txt for generic clock consumer properties.



Example:



	sdhci@84b0000 {

		sd-uhs-sdr50;

		sd-uhs-ddr50;

		sd-uhs-sdr104;

		sdhci,auto-cmd12;

		compatible = "brcm,bcm7216-sdhci",

			   "brcm,bcm7445-sdhci",

			   "brcm,sdhci-brcmstb";

		reg = <0x84b0000 0x260 0x84b0300 0x200>;

		reg-names = "host", "cfg";

		interrupts = <0x0 0x26 0x4>;

		interrupt-names = "sdio0_0";

		clocks = <&scmi_clk 245>;

		clock-names = "sw_sdio";

	};



	sdhci@84b1000 {

		mmc-ddr-1_8v;

		mmc-hs200-1_8v;

		mmc-hs400-1_8v;

		mmc-hs400-enhanced-strobe;

		supports-cqe;

		non-removable;

		bus-width = <0x8>;

		compatible = "brcm,bcm7216-sdhci",

			   "brcm,bcm7445-sdhci",

			   "brcm,sdhci-brcmstb";

		reg = <0x84b1000 0x260 0x84b1300 0x200>;

		reg-names = "host", "cfg";

		interrupts = <0x0 0x27 0x4>;

		interrupt-names = "sdio1_0";

		clocks = <&scmi_clk 245>;

		clock-names = "sw_sdio";

	};

Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmstb.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Broadcom BRCMSTB/BMIPS SDHCI Controller binding



maintainers:

  - Al Cooper <alcooperx@gmail.com>

  - Florian Fainelli <f.fainelli@gmail.com>



allOf:

  - $ref: mmc-controller.yaml#



properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - brcm,bcm7216-sdhci

          - const: brcm,bcm7445-sdhci

          - const: brcm,sdhci-brcmstb

      - items:

          - enum:

              - brcm,bcm7445-sdhci

          - const: brcm,sdhci-brcmstb

      - items:

          - enum:

              - brcm,bcm7425-sdhci

          - const: brcm,sdhci-brcmstb



  reg:

    minItems: 2



  reg-names:

    items:

      - const: host

      - const: cfg



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1

    description:

      handle to core clock for the sdhci controller.



  clock-names:

    items:

      - const: sw_sdio



  sdhci,auto-cmd12:

    type: boolean

    description: Specifies that controller should use auto CMD12



required:

  - compatible

  - reg

  - interrupts

  - clocks



unevaluatedProperties: false



examples:

  - |

    mmc@84b0000 {

      sd-uhs-sdr50;

      sd-uhs-ddr50;

      sd-uhs-sdr104;

      sdhci,auto-cmd12;

      compatible = "brcm,bcm7216-sdhci",

                   "brcm,bcm7445-sdhci",

                   "brcm,sdhci-brcmstb";

      reg = <0x84b0000 0x260>, <0x84b0300 0x200>;

      reg-names = "host", "cfg";

      interrupts = <0x0 0x26 0x4>;

      interrupt-names = "sdio0_0";

      clocks = <&scmi_clk 245>;

      clock-names = "sw_sdio";

    };



    mmc@84b1000 {

      mmc-ddr-1_8v;

      mmc-hs200-1_8v;

      mmc-hs400-1_8v;

      mmc-hs400-enhanced-strobe;

      supports-cqe;

      non-removable;

      bus-width = <0x8>;

      compatible = "brcm,bcm7216-sdhci",

           "brcm,bcm7445-sdhci",

            "brcm,sdhci-brcmstb";

      reg = <0x84b1000 0x260>, <0x84b1300 0x200>;

      reg-names = "host", "cfg";

      interrupts = <0x0 0x27 0x4>;

      interrupt-names = "sdio1_0";

      clocks = <&scmi_clk 245>;

      clock-names = "sw_sdio";

    };

Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt

+2 −0
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@@ -22,6 +22,8 @@ Required Properties: 
	  specific extensions.

	- "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7

	  specific extensions having an SMU.

	- "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific

	  extensions.



* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface

  unit (ciu) clock. This property is applicable only for Exynos5 SoC's and