Commit 11408ea5 authored by Tejas Upadhyay's avatar Tejas Upadhyay Committed by Maarten Lankhorst
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drm/i915/gen11: Disable cursor clock gating in HDR mode 



Display underrun in HDR mode when cursor is enabled.
RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
As per W/A 1604331009, Disable cursor clock gating in HDR mode.

Bspec : 33451

Changes since V6:
        - Address checkpatch warnings
        - Bit ordering
Changes since V5:
        - replace intel_de_read with intel_de_rmw - Jani
Changes since V4:
        - Added WA needed check - Ville
        - Replace BIT with REG_BIT - Ville
        - Add WA enable/disable support back which was
          added in V1 - Ville
Changes since V3:
        - Disable WA when not in HDR mode or cursor plane
          not active - Ville
        - Extract required args from crtc_state - Ville
        - Create HDR mode API using bdw_set_pipemisc ref - Ville
        - Tested with HDR video as well full setmode, WA
          applies and disables
Changes since V2:
        - Made it general gen11 WA
        - Removed WA needed check
        - Added cursor plane active check
        - Once WA enable, software will not disable
Changes since V1:
        - Modified way CLKGATE_DIS_PSL bit 28 was modified

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarTejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210929052442.2543054-1-tejaskumarx.surendrakumar.upadhyay@intel.com
parent dde98a57

drivers/gpu/drm/i915/display/intel_display.c

+32 −0
Original line number Diff line number Diff line
@@ -309,6 +309,15 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 
		               intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);

}



/* Wa_1604331009:icl,jsl,ehl */

static void

icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,

		       bool enable)

{

	intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS,

		     enable ? CURSOR_GATING_DIS : 0);

}



static bool

is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)

{
@@ -2451,6 +2460,19 @@ static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 
	return false;

}



static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);



	/* Wa_1604331009:icl,jsl,ehl */

	if (is_hdr_mode(crtc_state) &&

	    crtc_state->active_planes & BIT(PLANE_CURSOR) &&

	    DISPLAY_VER(dev_priv) == 11)

		return true;



	return false;

}



static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,

			    const struct intel_crtc_state *new_crtc_state)

{
@@ -2493,6 +2515,11 @@ static void intel_post_plane_update(struct intel_atomic_state *state, 
	if (needs_scalerclk_wa(old_crtc_state) &&

	    !needs_scalerclk_wa(new_crtc_state))

		icl_wa_scalerclkgating(dev_priv, pipe, false);



	if (needs_cursorclk_wa(old_crtc_state) &&

	    !needs_cursorclk_wa(new_crtc_state))

		icl_wa_cursorclkgating(dev_priv, pipe, false);



}



static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
@@ -2589,6 +2616,11 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, 
	    needs_scalerclk_wa(new_crtc_state))

		icl_wa_scalerclkgating(dev_priv, pipe, true);



	/* Wa_1604331009:icl,jsl,ehl */

	if (!needs_cursorclk_wa(old_crtc_state) &&

	    needs_cursorclk_wa(new_crtc_state))

		icl_wa_cursorclkgating(dev_priv, pipe, true);



	/*

	 * Vblank time updates from the shadow to live plane control register

	 * are blocked if the memory self-refresh mode is active at that

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -4239,6 +4239,7 @@ enum { 
#define   DUPS1_GATING_DIS		(1 << 15)

#define   DUPS2_GATING_DIS		(1 << 19)

#define   DUPS3_GATING_DIS		(1 << 23)

#define   CURSOR_GATING_DIS		REG_BIT(28)

#define   DPF_GATING_DIS		(1 << 10)

#define   DPF_RAM_GATING_DIS		(1 << 9)

#define   DPFR_GATING_DIS		(1 << 8)