Commit 113a031b authored by Jacob Pan's avatar Jacob Pan Committed by Joerg Roedel
Browse files

iommu/vt-d: Remove PASID supervisor request support 



There's no more usage, remove PASID supervisor support.

Suggested-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: default avatarJacob Pan <jacob.jun.pan@linux.intel.com>
Link: https://lore.kernel.org/r/20230331231137.1947675-3-jacob.jun.pan@linux.intel.com


Signed-off-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent a7050fbd

drivers/iommu/intel/pasid.c

+0 −43
Original line number Diff line number Diff line
@@ -335,15 +335,6 @@ static inline void pasid_set_fault_enable(struct pasid_entry *pe) 
	pasid_set_bits(&pe->val[0], 1 << 1, 0);

}



/*

 * Setup the SRE(Supervisor Request Enable) field (Bit 128) of a

 * scalable mode PASID entry.

 */

static inline void pasid_set_sre(struct pasid_entry *pe)

{

	pasid_set_bits(&pe->val[2], 1 << 0, 1);

}



/*

 * Setup the WPE(Write Protect Enable) field (Bit 132) of a

 * scalable mode PASID entry.
@@ -521,23 +512,6 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu, 
		return -EINVAL;

	}



	if (flags & PASID_FLAG_SUPERVISOR_MODE) {

#ifdef CONFIG_X86

		unsigned long cr0 = read_cr0();



		/* CR0.WP is normally set but just to be sure */

		if (unlikely(!(cr0 & X86_CR0_WP))) {

			pr_err("No CPU write protect!\n");

			return -EINVAL;

		}

#endif

		if (!ecap_srs(iommu->ecap)) {

			pr_err("No supervisor request support on %s\n",

			       iommu->name);

			return -EINVAL;

		}

	}



	if ((flags & PASID_FLAG_FL5LP) && !cap_fl5lp_support(iommu->cap)) {

		pr_err("No 5-level paging support for first-level on %s\n",

		       iommu->name);
@@ -560,10 +534,6 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu, 


	/* Setup the first level page table pointer: */

	pasid_set_flptr(pte, (u64)__pa(pgd));

	if (flags & PASID_FLAG_SUPERVISOR_MODE) {

		pasid_set_sre(pte);

		pasid_set_wpe(pte);

	}



	if (flags & PASID_FLAG_FL5LP)

		pasid_set_flpm(pte, 1);
@@ -658,12 +628,6 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu, 
	pasid_set_fault_enable(pte);

	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));



	/*

	 * Since it is a second level only translation setup, we should

	 * set SRE bit as well (addresses are expected to be GPAs).

	 */

	if (pasid != PASID_RID2PASID && ecap_srs(iommu->ecap))

		pasid_set_sre(pte);

	pasid_set_present(pte);

	spin_unlock(&iommu->lock);
@@ -700,13 +664,6 @@ int intel_pasid_setup_pass_through(struct intel_iommu *iommu, 
	pasid_set_translation_type(pte, PASID_ENTRY_PGTT_PT);

	pasid_set_fault_enable(pte);

	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));



	/*

	 * We should set SRE bit as well since the addresses are expected

	 * to be GPAs.

	 */

	if (ecap_srs(iommu->ecap))

		pasid_set_sre(pte);

	pasid_set_present(pte);

	spin_unlock(&iommu->lock);

drivers/iommu/intel/pasid.h

+0 −7
Original line number Diff line number Diff line
@@ -41,13 +41,6 @@ 
#define FLPT_DEFAULT_DID		1

#define NUM_RESERVED_DID		2



/*

 * The SUPERVISOR_MODE flag indicates a first level translation which

 * can be used for access to kernel addresses. It is valid only for

 * access to the kernel's static 1:1 mapping of physical memory — not

 * to vmalloc or even module mappings.

 */

#define PASID_FLAG_SUPERVISOR_MODE	BIT(0)

#define PASID_FLAG_NESTED		BIT(1)

#define PASID_FLAG_PAGE_SNOOP		BIT(2)