Commit 1129a0e5 authored Nov 12, 2024 by Marek Vasut Committed by Wentao Guan Mar 25, 2025

clk: imx8mp: Fix clkout1/2 support

stable inclusion
from stable-v6.6.76
commit a32da24ef8cccf4b390d16574fef9dbdd23eca8e
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IBW08Q

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a32da24ef8cccf4b390d16574fef9dbdd23eca8e



--------------------------------

[ Upstream commit a9b7c84d22fb1687d63ca2a386773015cf59436b ]

The CLKOUTn may be fed from PLL1/2/3, but the PLL1/2/3 has to be enabled
first by setting PLL_CLKE bit 11 in CCM_ANALOG_SYS_PLLn_GEN_CTRL register.
The CCM_ANALOG_SYS_PLLn_GEN_CTRL bit 11 is modeled by plln_out clock. Fix
the clock tree and place the clkout1/2 under plln_sel instead of plain plln
to let the clock subsystem correctly control the bit 11 and enable the PLL
in case the CLKOUTn is supplied by PLL1/2/3.

Fixes: 43896f56 ("clk: imx8mp: add clkout1/2 support")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20241112013718.333771-1-marex@denx.de


Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
(cherry picked from commit a32da24ef8cccf4b390d16574fef9dbdd23eca8e)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

parent 82ed9377

drivers/clk/imx/clk-imx8mp.c

+3 −2

Original line number	Diff line number	Diff line
		@@ -399,8 +399,9 @@ static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_r

		static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
		"dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
		"arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
		"dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
		"arm_pll_out", "sys_pll1_out", "sys_pll2_out",
		"sys_pll3_out", "dummy", "dummy", "osc_24m",
		"dummy", "osc_32k"};

		static struct clk_hw **hws;
		static struct clk_hw_onecell_data *clk_hw_data;