Commit 111a5a42 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'omap-for-v5.12/fixes-rc4-signed' of... 

Merge tag 'omap-for-v5.12/fixes-rc4-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes

More fixes for omaps for v5.12-rc cycle

Two fixes for hangs, mmc slot order fix, and a voltage typo fix:

- Remove unused duplicate sha2md5_fck clock node that can race with the
  OMAP4_SHA2MD5_CLKCTRL clock node for disable for unused clocks

- Add aliases for omap4/5 mmc to put the slots back into the right
  order again

- Fix typo for bionic voltage controllers that accidentally use mpu
  for all instances instead of mpu, core and iva

- Fix random hangs for droid4 caused by missing fix from TI Android
  kernel tree to do a dummy smc call on cpuidle wakeup path

* tag 'omap-for-v5.12/fixes-rc4-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP4: PM: update ROM return address for OSWR and OFF
  ARM: OMAP4: Fix PMIC voltage domains for bionic
  ARM: dts: Fix moving mmc devices with aliases for omap4 & 5
  ARM: dts: Drop duplicate sha2md5_fck to fix clk_disable race

Link: https://lore.kernel.org/r/pull-1616584662-702939@atomide.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 70a6062c b3d09a06

arch/arm/boot/dts/omap4.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -22,6 +22,11 @@ 
		i2c1 = &i2c2;

		i2c2 = &i2c3;

		i2c3 = &i2c4;

		mmc0 = &mmc1;

		mmc1 = &mmc2;

		mmc2 = &mmc3;

		mmc3 = &mmc4;

		mmc4 = &mmc5;

		serial0 = &uart1;

		serial1 = &uart2;

		serial2 = &uart3;

arch/arm/boot/dts/omap44xx-clocks.dtsi

+0 −8
Original line number Diff line number Diff line
@@ -770,14 +770,6 @@ 
		ti,max-div = <2>;

	};



	sha2md5_fck: sha2md5_fck@15c8 {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&l3_div_ck>;

		ti,bit-shift = <1>;

		reg = <0x15c8>;

	};



	usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

arch/arm/boot/dts/omap5.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -25,6 +25,11 @@ 
		i2c2 = &i2c3;

		i2c3 = &i2c4;

		i2c4 = &i2c5;

		mmc0 = &mmc1;

		mmc1 = &mmc2;

		mmc2 = &mmc3;

		mmc3 = &mmc4;

		mmc4 = &mmc5;

		serial0 = &uart1;

		serial1 = &uart2;

		serial2 = &uart3;

arch/arm/mach-omap2/omap-secure.c

+39 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
 */



#include <linux/arm-smccc.h>

#include <linux/cpu_pm.h>

#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/io.h>
@@ -20,6 +21,7 @@ 


#include "common.h"

#include "omap-secure.h"

#include "soc.h"



static phys_addr_t omap_secure_memblock_base;
@@ -213,3 +215,40 @@ void __init omap_secure_init(void) 
{

	omap_optee_init_check();

}



/*

 * Dummy dispatcher call after core OSWR and MPU off. Updates the ROM return

 * address after MMU has been re-enabled after CPU1 has been woken up again.

 * Otherwise the ROM code will attempt to use the earlier physical return

 * address that got set with MMU off when waking up CPU1. Only used on secure

 * devices.

 */

static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)

{

	switch (cmd) {

	case CPU_CLUSTER_PM_EXIT:

		omap_secure_dispatcher(OMAP4_PPA_SERVICE_0,

				       FLAG_START_CRITICAL,

				       0, 0, 0, 0, 0);

		break;

	default:

		break;

	}



	return NOTIFY_OK;

}



static struct notifier_block secure_notifier_block = {

	.notifier_call = cpu_notifier,

};



static int __init secure_pm_init(void)

{

	if (omap_type() == OMAP2_DEVICE_TYPE_GP || !soc_is_omap44xx())

		return 0;



	cpu_pm_register_notifier(&secure_notifier_block);



	return 0;

}

omap_arch_initcall(secure_pm_init);

arch/arm/mach-omap2/omap-secure.h

+1 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ 
#define OMAP5_DRA7_MON_SET_ACR_INDEX	0x107



/* Secure PPA(Primary Protected Application) APIs */

#define OMAP4_PPA_SERVICE_0		0x21

#define OMAP4_PPA_L2_POR_INDEX		0x23

#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX	0x25