Commit 109a357f authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: clean up some leftovers from bring up 



Some old registers leftover from pre-silicon.  No longer
relevant on real hardware.  Remove.

Reviewed-by: default avatarJames Zhu <James.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 892deb48

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_offset.h

+0 −2
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@@ -20753,8 +20753,6 @@ 








// addressBlock: nbio_nbif0_gdc_GDCDEC









// base address: 0xd0000000









#define regGDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL                                                          0x2ffc0eda









#define regGDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL_BASE_IDX                                                 5









#define regGDC1_NGDC_SDP_PORT_CTRL                                                                      0x2ffc0ee2









#define regGDC1_NGDC_SDP_PORT_CTRL_BASE_IDX                                                             5









#define regGDC1_SHUB_REGS_IF_CTL                                                                        0x2ffc0ee3

























drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h



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/*









 * Copyright (C) 2020  Advanced Micro Devices, Inc.









 *








@@ -108541,17 +108540,6 @@























// addressBlock: nbio_nbif0_gdc_GDCDEC









//GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL









#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN0_FAST_WRITE_RESPONSE_EN__SHIFT                             0x0









#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN1_FAST_WRITE_RESPONSE_EN__SHIFT                             0x1









#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN2_FAST_WRITE_RESPONSE_EN__SHIFT                             0x2









#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN3_FAST_WRITE_RESPONSE_EN__SHIFT                             0x3









#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__FWR_NORMAL_ARB_MODE__SHIFT                                       0x10









#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN0_FAST_WRITE_RESPONSE_EN_MASK                               0x00000001L









#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN1_FAST_WRITE_RESPONSE_EN_MASK                               0x00000002L









#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN2_FAST_WRITE_RESPONSE_EN_MASK                               0x00000004L









#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN3_FAST_WRITE_RESPONSE_EN_MASK                               0x00000008L









#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__FWR_NORMAL_ARB_MODE_MASK                                         0x00010000L









//GDC1_NGDC_SDP_PORT_CTRL









#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT                                                 0x0









#define GDC1_NGDC_SDP_PORT_CTRL__NGDC_OBFF_HW_URGENT_EARLY_WAKEUP_EN__SHIFT                                   0xf