Commit 1089877a authored by Biju Das's avatar Biju Das Committed by Jakub Kicinski
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ravb: Add RZ/G2L MII interface support



EMAC IP found on RZ/G2L Gb ethernet supports MII interface.
This patch adds support for selecting MII interface mode.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarSergey Shtylyov <s.shtylyov@omp.ru>
Link: https://lore.kernel.org/r/20220914192604.265859-1-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent a4abfa62
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+8 −0
Original line number Diff line number Diff line
@@ -189,6 +189,7 @@ enum ravb_reg {
	PSR	= 0x0528,
	PIPR	= 0x052c,
	CXR31	= 0x0530,	/* RZ/G2L only */
	CXR35	= 0x0540,	/* RZ/G2L only */
	MPR	= 0x0558,
	PFTCR	= 0x055c,
	PFRCR	= 0x0560,
@@ -965,6 +966,13 @@ enum CXR31_BIT {
	CXR31_SEL_LINK1	= 0x00000008,
};

enum CXR35_BIT {
	CXR35_SEL_XMII		= 0x00000003,
	CXR35_SEL_XMII_RGMII	= 0x00000000,
	CXR35_SEL_XMII_MII	= 0x00000002,
	CXR35_HALFCYC_CLKSW	= 0xffff0000,
};

enum CSR0_BIT {
	CSR0_TPE	= 0x00000010,
	CSR0_RPE	= 0x00000020,
+7 −1
Original line number Diff line number Diff line
@@ -540,7 +540,13 @@ static void ravb_emac_init_gbeth(struct net_device *ndev)
	/* E-MAC interrupt enable register */
	ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);

	ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, CXR31_SEL_LINK0);
	if (priv->phy_interface == PHY_INTERFACE_MODE_MII) {
		ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0);
		ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);
	} else {
		ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
			    CXR31_SEL_LINK0);
	}
}

static void ravb_emac_init_rcar(struct net_device *ndev)