Commit 10694700 authored by Michael Riesch's avatar Michael Riesch Committed by Hans Verkuil
Browse files

media: v4l2-mediabus: add support for dual edge sampling 



Some devices support sampling of the parallel data at both edges of the
interface pixel clock in order to reduce the pixel clock by two.
Add a mediabus flag that represents this feature.

Signed-off-by: default avatarMichael Riesch <michael.riesch@wolfvision.net>
Reviewed-by: default avatarJacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
parent 55f6f743

drivers/media/v4l2-core/v4l2-fwnode.c

+19 −4
Original line number Diff line number Diff line
@@ -298,10 +298,25 @@ v4l2_fwnode_endpoint_parse_parallel_bus(struct fwnode_handle *fwnode, 


	if (!fwnode_property_read_u32(fwnode, "pclk-sample", &v)) {

		flags &= ~(V4L2_MBUS_PCLK_SAMPLE_RISING |

			   V4L2_MBUS_PCLK_SAMPLE_FALLING);

		flags |= v ? V4L2_MBUS_PCLK_SAMPLE_RISING :

			V4L2_MBUS_PCLK_SAMPLE_FALLING;

		pr_debug("pclk-sample %s\n", v ? "high" : "low");

			   V4L2_MBUS_PCLK_SAMPLE_FALLING |

			   V4L2_MBUS_PCLK_SAMPLE_DUALEDGE);

		switch (v) {

		case 0:

			flags |= V4L2_MBUS_PCLK_SAMPLE_FALLING;

			pr_debug("pclk-sample low\n");

			break;

		case 1:

			flags |= V4L2_MBUS_PCLK_SAMPLE_RISING;

			pr_debug("pclk-sample high\n");

			break;

		case 2:

			flags |= V4L2_MBUS_PCLK_SAMPLE_DUALEDGE;

			pr_debug("pclk-sample dual edge\n");

			break;

		default:

			pr_warn("invalid argument for pclk-sample");

			break;

		}

	}



	if (!fwnode_property_read_u32(fwnode, "data-active", &v)) {

include/media/v4l2-mediabus.h

+9 −8
Original line number Diff line number Diff line
@@ -54,17 +54,18 @@ 
#define V4L2_MBUS_VSYNC_ACTIVE_LOW		BIT(5)

#define V4L2_MBUS_PCLK_SAMPLE_RISING		BIT(6)

#define V4L2_MBUS_PCLK_SAMPLE_FALLING		BIT(7)

#define V4L2_MBUS_DATA_ACTIVE_HIGH		BIT(8)

#define V4L2_MBUS_DATA_ACTIVE_LOW		BIT(9)

#define V4L2_MBUS_PCLK_SAMPLE_DUALEDGE		BIT(8)

#define V4L2_MBUS_DATA_ACTIVE_HIGH		BIT(9)

#define V4L2_MBUS_DATA_ACTIVE_LOW		BIT(10)

/* FIELD = 0/1 - Field1 (odd)/Field2 (even) */

#define V4L2_MBUS_FIELD_EVEN_HIGH		BIT(10)

#define V4L2_MBUS_FIELD_EVEN_HIGH		BIT(11)

/* FIELD = 1/0 - Field1 (odd)/Field2 (even) */

#define V4L2_MBUS_FIELD_EVEN_LOW		BIT(11)

#define V4L2_MBUS_FIELD_EVEN_LOW		BIT(12)

/* Active state of Sync-on-green (SoG) signal, 0/1 for LOW/HIGH respectively. */

#define V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH		BIT(12)

#define V4L2_MBUS_VIDEO_SOG_ACTIVE_LOW		BIT(13)

#define V4L2_MBUS_DATA_ENABLE_HIGH		BIT(14)

#define V4L2_MBUS_DATA_ENABLE_LOW		BIT(15)

#define V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH		BIT(13)

#define V4L2_MBUS_VIDEO_SOG_ACTIVE_LOW		BIT(14)

#define V4L2_MBUS_DATA_ENABLE_HIGH		BIT(15)

#define V4L2_MBUS_DATA_ENABLE_LOW		BIT(16)



/* Serial flags */

/* Clock non-continuous mode support. */