Commit 10507130 authored by Piotr Kwapulinski's avatar Piotr Kwapulinski Committed by David S. Miller
Browse files

i40e: add support for PTP external synchronization clock 



Add support for external synchronization clock via GPIOs.
1PPS signals are handled via the dedicated 3 GPIOs: SDP3_2,
SDP3_3 and GPIO_4.
Previously it was not possible to use the external PTP
synchronization clock.
All possible HW configurations are supported.
	SDP3_2,	SDP3_3,	GPIO_4
	off,	off,	off
	off,	in_A,	off
	off,	out_A,	off
	off,	in_B,	off
	off,	out_B,	off
	in_A,	off,	off
	in_A,	in_B,	off
	in_A,	out_B,	off
	out_A,	off,	off
	out_A,	in_B,	off
	in_B,	off,	off
	in_B,	in_A,	off
	in_B,	out_A,	off
	out_B,	off,	off
	out_B,	in_A,	off
	off,	off,	in_A
	off,	out_A,	in_A
	off,	in_B,	in_A
	off,	out_B,	in_A
	out_A,	off,	in_A
	out_A,	in_B,	in_A
	in_B,	off,	in_A
	in_B,	out_A,	in_A
	out_B,	off,	in_A
	off,	off,	out_A
	off,	in_A,	out_A
	off,	in_B,	out_A
	off,	out_B,	out_A
	in_A,	off,	out_A
	in_A,	in_B,	out_A
	in_A,	out_B,	out_A
	in_B,	off,	out_A
	in_B,	in_A,	out_A
	out_B,	off,	out_A
	out_B,	in_A,	out_A
	off,	off,	in_B
	off,	in_A,	in_B
	off,	out_A,	in_B
	off,	out_B,	in_B
	in_A,	off,	in_B
	in_A,	out_B,	in_B
	out_A,	off,	in_B
	out_B,	off,	in_B
	out_B,	in_A,	in_B
	off,	off,	out_B
	off,	in_A,	out_B
	off,	out_A,	out_B
	off,	in_B,	out_B
	in_A,	off,	out_B
	in_A,	in_B,	out_B
	out_A,	off,	out_B
	out_A,	in_B,	out_B
	in_B,	off,	out_B
	in_B,	in_A,	out_B
	in_B,	out_A,	out_B

Tested with oscilloscope, 1PPS generator and ts2phc.

Reviewed-by: default avatarAleksandr Loktionov <aleksandr.loktionov@intel.com>
Reviewed-by: default avatarArkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: default avatarPiotr Kwapulinski <piotr.kwapulinski@intel.com>
Tested-by: default avatarAshish K <ashishx.k@intel.com>
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ac6627a2

drivers/net/ethernet/intel/i40e/i40e.h

+78 −0
Original line number Diff line number Diff line
@@ -428,6 +428,8 @@ struct i40e_channel { 
	struct i40e_vsi *parent_vsi;

};



struct i40e_ptp_pins_settings;



static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch)

{

	return !!ch->fwd;
@@ -644,12 +646,83 @@ struct i40e_pf { 
	struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */

	struct i40e_dcbx_config tmp_cfg;



/* GPIO defines used by PTP */

#define I40E_SDP3_2			18

#define I40E_SDP3_3			19

#define I40E_GPIO_4			20

#define I40E_LED2_0			26

#define I40E_LED2_1			27

#define I40E_LED3_0			28

#define I40E_LED3_1			29

#define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \

	(1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)

#define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \

	(1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)

#define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \

	(0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)

#define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \

	(1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)

#define I40E_GLGEN_GPIO_CTL_RESERVED	BIT(2)

#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \

	(1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)

#define I40E_GLGEN_GPIO_CTL_DIR_OUT \

	(1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)

#define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \

	(1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)

#define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \

	(1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)

#define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \

	(3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)

#define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \

	(4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)

#define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \

	(0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)

#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \

	(1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)

#define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \

	(I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \

	 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \

	 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)

#define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \

	(I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \

	 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \

	 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)

#define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \

	(I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \

	 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \

	 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \

	 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)

#define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \

	(I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \

	 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \

	 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \

	 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)

#define I40E_GLGEN_GPIO_CTL_LED_INIT \

	(I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \

	 I40E_GLGEN_GPIO_CTL_DIR_OUT | \

	 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \

	 I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \

	 I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \

	 I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN)

#define I40E_PRTTSYN_AUX_1_INSTNT \

	(1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)

#define I40E_PRTTSYN_AUX_0_OUT_ENABLE \

	(1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)

#define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD	(3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)

#define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \

	(I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD)

#define I40E_PTP_HALF_SECOND		500000000LL /* nano seconds */

#define I40E_PTP_2_SEC_DELAY		2



	struct ptp_clock *ptp_clock;

	struct ptp_clock_info ptp_caps;

	struct sk_buff *ptp_tx_skb;

	unsigned long ptp_tx_start;

	struct hwtstamp_config tstamp_config;

	struct timespec64 ptp_prev_hw_time;

	struct work_struct ptp_pps_work;

	struct work_struct ptp_extts0_work;

	struct work_struct ptp_extts1_work;

	ktime_t ptp_reset_start;

	struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */

	u32 ptp_adj_mult;
@@ -657,10 +730,14 @@ struct i40e_pf { 
	u32 tx_hwtstamp_skipped;

	u32 rx_hwtstamp_cleared;

	u32 latch_event_flags;

	u64 ptp_pps_start;

	u32 pps_delay;

	spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */

	struct ptp_pin_desc ptp_pin[3];

	unsigned long latch_events[4];

	bool ptp_tx;

	bool ptp_rx;

	struct i40e_ptp_pins_settings *ptp_pins;

	u16 rss_table_size; /* HW RSS table size */

	u32 max_bw;

	u32 min_bw;
@@ -1169,6 +1246,7 @@ void i40e_ptp_save_hw_time(struct i40e_pf *pf); 
void i40e_ptp_restore_hw_time(struct i40e_pf *pf);

void i40e_ptp_init(struct i40e_pf *pf);

void i40e_ptp_stop(struct i40e_pf *pf);

int i40e_ptp_alloc_pins(struct i40e_pf *pf);

int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);

i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);

i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);

drivers/net/ethernet/intel/i40e/i40e_main.c

+24 −4
Original line number Diff line number Diff line
@@ -4079,10 +4079,13 @@ static irqreturn_t i40e_intr(int irq, void *data) 
	if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {

		u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);



		if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {

			icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;

		if (prttsyn_stat & I40E_PRTTSYN_STAT_0_EVENT0_MASK)

			schedule_work(&pf->ptp_extts0_work);



		if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK)

			i40e_ptp_tx_hwtstamp(pf);

		}



		icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;

	}



	/* If a critical error is pending we have no choice but to reset the
@@ -15167,6 +15170,22 @@ static int i40e_init_recovery_mode(struct i40e_pf *pf, struct i40e_hw *hw) 
	return err;

}



/**

 * i40e_set_subsystem_device_id - set subsystem device id

 * @hw: pointer to the hardware info

 *

 * Set PCI subsystem device id either from a pci_dev structure or

 * a specific FW register.

 **/

static inline void i40e_set_subsystem_device_id(struct i40e_hw *hw)

{

	struct pci_dev *pdev = ((struct i40e_pf *)hw->back)->pdev;



	hw->subsystem_device_id = pdev->subsystem_device ?

		pdev->subsystem_device :

		(ushort)(rd32(hw, I40E_PFPCI_SUBSYSID) & USHRT_MAX);

}



/**

 * i40e_probe - Device initialization routine

 * @pdev: PCI device information struct
@@ -15262,7 +15281,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 
	hw->device_id = pdev->device;

	pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);

	hw->subsystem_vendor_id = pdev->subsystem_vendor;

	hw->subsystem_device_id = pdev->subsystem_device;

	i40e_set_subsystem_device_id(hw);

	hw->bus.device = PCI_SLOT(pdev->devfn);

	hw->bus.func = PCI_FUNC(pdev->devfn);

	hw->bus.bus_id = pdev->bus->number;
@@ -15442,6 +15461,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 
	if (is_valid_ether_addr(hw->mac.port_addr))

		pf->hw_features |= I40E_HW_PORT_ID_VALID;



	i40e_ptp_alloc_pins(pf);

	pci_set_drvdata(pdev, pf);

	pci_save_state(pdev);

drivers/net/ethernet/intel/i40e/i40e_ptp.c

+740 −16

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/intel/i40e/i40e_register.h

+29 −0
Original line number Diff line number Diff line
@@ -182,11 +182,20 @@ 
#define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)

#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3

#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)

#define I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT 4

#define I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT 5

#define I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT 6

#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7

#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK I40E_MASK(0x7, I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)

#define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11

#define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12

#define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)

#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT  19

#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK   I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)

#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20

#define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */

#define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5

#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6

#define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */

#define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */

#define I40E_GLGEN_MSCA_MDIADD_SHIFT 0
@@ -540,6 +549,7 @@ 
#define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12

#define I40E_PF_PCI_CIAD 0x0009C100 /* Reset: FLR */

#define I40E_PRTPM_EEE_STAT 0x001E4320 /* Reset: GLOBR */

#define I40E_PFPCI_SUBSYSID 0x000BE100 /* Reset: PCIR */

#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30

#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT)

#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31
@@ -742,6 +752,8 @@ 
#define I40E_PRTTSYN_CTL0 0x001E4200 /* Reset: GLOBR */

#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1

#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT)

#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT 2

#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT)

#define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8

#define I40E_PRTTSYN_CTL0_PF_ID_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL0_PF_ID_SHIFT)

#define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31
@@ -760,7 +772,10 @@ 
#define I40E_PRTTSYN_INC_L 0x001E4040 /* Reset: GLOBR */

#define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */

#define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */

#define I40E_PRTTSYN_RXTIME_L_MAX_INDEX 3

#define I40E_PRTTSYN_STAT_0 0x001E4220 /* Reset: GLOBR */

#define I40E_PRTTSYN_STAT_0_EVENT0_SHIFT 0

#define I40E_PRTTSYN_STAT_0_EVENT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT0_SHIFT)

#define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4

#define I40E_PRTTSYN_STAT_0_TXTIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TXTIME_SHIFT)

#define I40E_PRTTSYN_STAT_1 0x00085140 /* Reset: CORER */
@@ -768,6 +783,20 @@ 
#define I40E_PRTTSYN_TIME_L 0x001E4100 /* Reset: GLOBR */

#define I40E_PRTTSYN_TXTIME_H 0x001E41E0 /* Reset: GLOBR */

#define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */

#define I40E_PRTTSYN_EVNT_H(_i) (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */

#define I40E_PRTTSYN_EVNT_L(_i) (0x001E4080 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */

#define I40E_PRTTSYN_AUX_0(_i) (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */

#define I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT 0

#define I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT 1

#define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16

#define I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT 17

#define I40E_PRTTSYN_AUX_0_PTPFLAG_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT)

#define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */

#define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0

#define I40E_PRTTSYN_TGT_H(_i) (0x001E4180 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */

#define I40E_PRTTSYN_TGT_L(_i) (0x001E4140 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */

#define I40E_PRTTSYN_CLKO(_i) (0x001E4240 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */

#define I40E_PRTTSYN_ADJ 0x001E4280 /* Reset: GLOBR */

#define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */

#define I40E_GL_MDET_RX_FUNCTION_SHIFT 0

#define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT)