Commit 100e58c7 authored by Tony Luck's avatar Tony Luck Committed by Quanxian Wang
Browse files

x86/cpu: Add several Intel server CPU model numbers 

mainline inclusion
from mainline-v6.1-rc4
commit 7beade0d
category: feature
feature: Intel server CPU model numbers
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I6M81K
CVE: N/A
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/


commit/?id=7beade0d

Intel-SIG: commit 7beade0d ("x86/cpu: Add several Intel server CPU model numbers")
-------------------------------------

x86/cpu: Add several Intel server CPU model numbers

These servers are all on the public versions of the roadmap. The model
numbers for Grand Ridge, Granite Rapids, and Sierra Forest were included
in the September 2022 edition of the Instruction Set Extensions document.

Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Acked-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/r/20221103203310.5058-1-tony.luck@intel.com


Signed-off-by: default avatarQuanxian Wang <quanxian.wang@intel.com>
parent b3620df5

arch/x86/include/asm/intel-family.h

+10 −1
Original line number Diff line number Diff line
@@ -103,10 +103,15 @@ 


#define INTEL_FAM6_SAPPHIRERAPIDS_X	0x8F	/* Golden Cove */



#define INTEL_FAM6_EMERALDRAPIDS_X	0xCF



#define INTEL_FAM6_GRANITERAPIDS_X	0xAD

#define INTEL_FAM6_GRANITERAPIDS_D	0xAE



#define INTEL_FAM6_ALDERLAKE		0x97	/* Golden Cove / Gracemont */

#define INTEL_FAM6_ALDERLAKE_L		0x9A	/* Golden Cove / Gracemont */



/* "Small Core" Processors (Atom) */

/* "Small Core" Processors (Atom/E-Core) */



#define INTEL_FAM6_ATOM_BONNELL		0x1C /* Diamondville, Pineview */

#define INTEL_FAM6_ATOM_BONNELL_MID	0x26 /* Silverthorne, Lincroft */
@@ -133,6 +138,10 @@ 
#define INTEL_FAM6_ATOM_TREMONT		0x96 /* Elkhart Lake */

#define INTEL_FAM6_ATOM_TREMONT_L	0x9C /* Jasper Lake */



#define INTEL_FAM6_SIERRAFOREST_X	0xAF



#define INTEL_FAM6_GRANDRIDGE		0xB6



/* Xeon Phi */



#define INTEL_FAM6_XEON_PHI_KNL		0x57 /* Knights Landing */