Commit 1001f2a1 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: support rom clockgating related function for NV family 



Add functions to support enable/disable rom clock gating and get rom
clock gating status.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0bf7f2dc

drivers/gpu/drm/amd/amdgpu/nv.c

+4 −0
Original line number Diff line number Diff line
@@ -1144,6 +1144,8 @@ static int nv_common_set_clockgating_state(void *handle, 
				state == AMD_CG_STATE_GATE);

		adev->hdp.funcs->update_clock_gating(adev,

				state == AMD_CG_STATE_GATE);

		adev->smuio.funcs->update_rom_clock_gating(adev,

				state == AMD_CG_STATE_GATE);

		break;

	default:

		break;
@@ -1169,6 +1171,8 @@ static void nv_common_get_clockgating_state(void *handle, u32 *flags) 


	adev->hdp.funcs->get_clock_gating_state(adev, flags);



	adev->smuio.funcs->get_clock_gating_state(adev, flags);



	return;

}

drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.c

+36 −0
Original line number Diff line number Diff line
@@ -35,7 +35,43 @@ static u32 smuio_v11_0_6_get_rom_data_offset(struct amdgpu_device *adev) 
	return SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);

}



static void smuio_v11_0_6_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)

{

	u32 def, data;



	/* enable/disable ROM CG is not supported on APU */

	if (adev->flags & AMD_IS_APU)

		return;



	def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);



	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))

		data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |

			CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);

	else

		data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |

			CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;



	if (def != data)

		WREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0, data);

}



static void smuio_v11_0_6_get_clock_gating_state(struct amdgpu_device *adev, u32 *flags)

{

	u32 data;



	/* CGTT_ROM_CLK_CTRL0 is not available for APU */

	if (adev->flags & AMD_IS_APU)

		return;



	data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);

	if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))

		*flags |= AMD_CG_SUPPORT_ROM_MGCG;

}



const struct amdgpu_smuio_funcs smuio_v11_0_6_funcs = {

	.get_rom_index_offset = smuio_v11_0_6_get_rom_index_offset,

	.get_rom_data_offset = smuio_v11_0_6_get_rom_data_offset,

	.update_rom_clock_gating = smuio_v11_0_6_update_rom_clock_gating,

	.get_clock_gating_state = smuio_v11_0_6_get_clock_gating_state,

};