Loading arch/arc/Kconfig +6 −0 Original line number Diff line number Diff line Loading @@ -474,6 +474,12 @@ config ARC_IRQ_NO_AUTOSAVE This is programmable and can be optionally disabled in which case software INTERRUPT_PROLOGUE/EPILGUE do the needed work config ARC_LPB_DISABLE bool "Disable loop buffer (LPB)" help On HS cores, loop buffer (LPB) is programmable in runtime and can be optionally disabled. endif # ISA_ARCV2 endmenu # "ARC CPU Configuration" Loading arch/arc/kernel/head.S +8 −0 Original line number Diff line number Diff line Loading @@ -59,6 +59,14 @@ bclr r5, r5, STATUS_AD_BIT #endif kflag r5 #ifdef CONFIG_ARC_LPB_DISABLE lr r5, [ARC_REG_LPB_BUILD] breq r5, 0, 1f ; LPB doesn't exist mov r5, 1 sr r5, [ARC_REG_LPB_CTRL] 1: #endif /* CONFIG_ARC_LPB_DISABLE */ #endif ; Config DSP_CTRL properly, so kernel may use integer multiply, ; multiply-accumulate, and divide operations Loading Loading
arch/arc/Kconfig +6 −0 Original line number Diff line number Diff line Loading @@ -474,6 +474,12 @@ config ARC_IRQ_NO_AUTOSAVE This is programmable and can be optionally disabled in which case software INTERRUPT_PROLOGUE/EPILGUE do the needed work config ARC_LPB_DISABLE bool "Disable loop buffer (LPB)" help On HS cores, loop buffer (LPB) is programmable in runtime and can be optionally disabled. endif # ISA_ARCV2 endmenu # "ARC CPU Configuration" Loading
arch/arc/kernel/head.S +8 −0 Original line number Diff line number Diff line Loading @@ -59,6 +59,14 @@ bclr r5, r5, STATUS_AD_BIT #endif kflag r5 #ifdef CONFIG_ARC_LPB_DISABLE lr r5, [ARC_REG_LPB_BUILD] breq r5, 0, 1f ; LPB doesn't exist mov r5, 1 sr r5, [ARC_REG_LPB_CTRL] 1: #endif /* CONFIG_ARC_LPB_DISABLE */ #endif ; Config DSP_CTRL properly, so kernel may use integer multiply, ; multiply-accumulate, and divide operations Loading