Commit 0ff0af18 authored Jan 23, 2022 by Dan Williams

cxl/core/port: Rename bus.c to port.c

Given it is dominated by port infrastructure, and will only acquire
more, rename bus.c to port.c.

Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Link: https://lore.kernel.org/r/164298416136.3018233.15442880970000855425.stgit@dwillia2-desk3.amr.corp.intel.com

Signed-off-by: Dan Williams <dan.j.williams@intel.com>

parent c57cae78

Documentation/driver-api/cxl/memory-devices.rst

+2 −2

Original line number	Diff line number	Diff line
		@@ -36,10 +36,10 @@ CXL Core
		.. kernel-doc:: drivers/cxl/cxl.h
		:internal:

		.. kernel-doc:: drivers/cxl/core/bus.c
		.. kernel-doc:: drivers/cxl/core/port.c
		:doc: cxl core

		.. kernel-doc:: drivers/cxl/core/bus.c
		.. kernel-doc:: drivers/cxl/core/port.c
		:identifiers:

		.. kernel-doc:: drivers/cxl/core/pmem.c

drivers/cxl/core/Makefile

+1 −1

Original line number	Diff line number	Diff line
		@@ -2,7 +2,7 @@
		obj-$(CONFIG_CXL_BUS) += cxl_core.o

		ccflags-y += -I$(srctree)/drivers/cxl
		cxl_core-y := bus.o
		cxl_core-y := port.o
		cxl_core-y += pmem.o
		cxl_core-y += regs.o
		cxl_core-y += memdev.o

drivers/cxl/core/bus.c→drivers/cxl/core/port.c

+0 −0

File moved.

tools/testing/cxl/Kbuild

+1 −1

Original line number	Diff line number	Diff line
		@@ -25,7 +25,7 @@ cxl_pmem-y += config_check.o

		obj-m += cxl_core.o

		cxl_core-y := $(CXL_CORE_SRC)/bus.o
		cxl_core-y := $(CXL_CORE_SRC)/port.o
		cxl_core-y += $(CXL_CORE_SRC)/pmem.o
		cxl_core-y += $(CXL_CORE_SRC)/regs.o
		cxl_core-y += $(CXL_CORE_SRC)/memdev.o