Unverified Commit 0fc31598 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!12266 [OLK-5.10] AMD Genoa and Turin iommu patches backport for OLK-5.10 

Merge Pull Request from: @PvsNarasimha 
 
Backported patches to support the following AMD's Turin and Genoa system feature:

IOMMU interrupt generation in X2APIC mode 
 
Link:https://gitee.com/openeuler/kernel/pulls/12266

 

Reviewed-by: default avatarLi Nan <linan122@huawei.com>
Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Reviewed-by: default avatarZhang Jianhua <chris.zjh@huawei.com>
Reviewed-by: default avatarWenkuan Wang <wenkuan.wang@amd.com>
Signed-off-by: default avatarLi Nan <linan122@huawei.com>
Acked-by: default avatarXie XiuQi <xiexiuqi@huawei.com>
parents 211c4ef8 a33f2e49

arch/x86/include/asm/apic.h

+11 −9
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <asm/msr.h>

#include <asm/hardirq.h>

#include <asm/io.h>

#include <linux/kabi.h>



#define ARCH_APICTIMER_STOPS_ON_C3	1
@@ -298,11 +299,11 @@ struct apic { 
	void	(*send_IPI_all)(int vector);

	void	(*send_IPI_self)(int vector);



	/* dest_logical is used by the IPI functions */

	u32	dest_logical;

	_KABI_DEPRECATE(u32, dest_logical);

	u32	disable_esr;

	u32	irq_delivery_mode;

	u32	irq_dest_mode;



	_KABI_DEPRECATE(u32, irq_delivery_mode);

	_KABI_DEPRECATE(u32, irq_dest_mode);



	u32	(*calc_dest_apicid)(unsigned int cpu);
@@ -347,6 +348,9 @@ struct apic { 
	int (*x86_32_early_logical_apicid)(int cpu);

#endif

	char	*name;



	KABI_EXTEND(enum apic_delivery_modes delivery_mode)

	KABI_EXTEND(bool dest_mode_logical)

};



/*
@@ -513,12 +517,10 @@ static inline void apic_smt_update(void) { } 
#endif



struct msi_msg;

struct irq_cfg;



#ifdef CONFIG_PCI_MSI

void x86_vector_msi_compose_msg(struct irq_data *data, struct msi_msg *msg);

#else

# define x86_vector_msi_compose_msg NULL

#endif

extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,

				  bool dmar);



extern void ioapic_zap_locks(void);

arch/x86/include/asm/apicdef.h

+7 −9
Original line number Diff line number Diff line
@@ -432,15 +432,13 @@ struct local_apic { 
 #define BAD_APICID 0xFFFFu

#endif



enum ioapic_irq_destination_types {

	dest_Fixed		= 0,

	dest_LowestPrio		= 1,

	dest_SMI		= 2,

	dest__reserved_1	= 3,

	dest_NMI		= 4,

	dest_INIT		= 5,

	dest__reserved_2	= 6,

	dest_ExtINT		= 7

enum apic_delivery_modes {

	APIC_DELIVERY_MODE_FIXED	= 0,

	APIC_DELIVERY_MODE_LOWESTPRIO   = 1,

	APIC_DELIVERY_MODE_SMI		= 2,

	APIC_DELIVERY_MODE_NMI		= 4,

	APIC_DELIVERY_MODE_INIT		= 5,

	APIC_DELIVERY_MODE_EXTINT	= 7,

};



#endif /* _ASM_X86_APICDEF_H */

arch/x86/include/asm/hw_irq.h

+1 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ enum irq_alloc_type { 
	X86_IRQ_ALLOC_TYPE_PCI_MSI,

	X86_IRQ_ALLOC_TYPE_PCI_MSIX,

	X86_IRQ_ALLOC_TYPE_DMAR,

	X86_IRQ_ALLOC_TYPE_AMDVI,

	X86_IRQ_ALLOC_TYPE_UV,

	X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT,

	X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT,

arch/x86/include/asm/msi.h

+52 −0
Original line number Diff line number Diff line
@@ -9,4 +9,56 @@ typedef struct irq_alloc_info msi_alloc_info_t; 
int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,

		    msi_alloc_info_t *arg);



/* Structs and defines for the X86 specific MSI message format */



typedef struct x86_msi_data {

	union {

		struct {

			u32	vector			:  8,

				delivery_mode		:  3,

				dest_mode_logical	:  1,

				reserved		:  2,

				active_low		:  1,

				is_level		:  1;

		};

		u32	dmar_subhandle;

	};

} __attribute__ ((packed)) arch_msi_msg_data_t;

#define arch_msi_msg_data	x86_msi_data



typedef struct x86_msi_addr_lo {

	union {

		struct {

			u32	reserved_0		:  2,

				dest_mode_logical	:  1,

				redirect_hint		:  1,

				reserved_1		:  8,

				destid_0_7		:  8,

				base_address		: 12;

		};

		struct {

			u32	dmar_reserved_0		:  2,

				dmar_index_15		:  1,

				dmar_subhandle_valid	:  1,

				dmar_format		:  1,

				dmar_index_0_14		: 15,

				dmar_base_address	: 12;

		};

	};

} __attribute__ ((packed)) arch_msi_msg_addr_lo_t;

#define arch_msi_msg_addr_lo	x86_msi_addr_lo



#define X86_MSI_BASE_ADDRESS_LOW	(0xfee00000 >> 20)



typedef struct x86_msi_addr_hi {

	u32	reserved		:  8,

		destid_8_31		: 24;

} __attribute__ ((packed)) arch_msi_msg_addr_hi_t;

#define arch_msi_msg_addr_hi	x86_msi_addr_hi



#define X86_MSI_BASE_ADDRESS_HIGH	(0)



struct msi_msg;

u32 x86_msi_msg_get_destid(struct msi_msg *msg, bool extid);



#endif /* _ASM_X86_MSI_H */

arch/x86/kernel/apic/apic.c

+36 −1
Original line number Diff line number Diff line
@@ -1594,7 +1594,7 @@ static void setup_local_APIC(void) 
	apic->init_apic_ldr();



#ifdef CONFIG_X86_32

	if (apic->dest_logical) {

	if (apic->dest_mode_logical) {

		int logical_apicid, ldr_apicid;



		/*
@@ -2488,6 +2488,41 @@ int hard_smp_processor_id(void) 
	return read_apic_id();

}



void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,

			   bool dmar)

{

	memset(msg, 0, sizeof(*msg));



	msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;

	msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical;

	msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF;



	msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED;

	msg->arch_data.vector = cfg->vector;



	msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;

	/*

	 * Only the IOMMU itself can use the trick of putting destination

	 * APIC ID into the high bits of the address. Anything else would

	 * just be writing to memory if it tried that, and needs IR to

	 * address higher APIC IDs.

	 */

	if (dmar)

		msg->arch_addr_hi.destid_8_31 = cfg->dest_apicid >> 8;

	else

		WARN_ON_ONCE(cfg->dest_apicid > 0xFF);

}



u32 x86_msi_msg_get_destid(struct msi_msg *msg, bool extid)

{

	u32 dest = msg->arch_addr_lo.destid_0_7;



	if (extid)

		dest |= msg->arch_addr_hi.destid_8_31 << 8;

	return dest;

}

EXPORT_SYMBOL_GPL(x86_msi_msg_get_destid);



/*

 * Override the generic EOI implementation with an optimized version.

 * Only called during early boot when only one CPU is active and with