Commit 0f6563a3 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/asm' into for-next/core 

* for-next/asm:
  arm64: uaccess: remove unnecessary earlyclobber
  arm64: uaccess: permit put_{user,kernel} to use zero register
  arm64: uaccess: permit __smp_store_release() to use zero register
  arm64: atomics: lse: improve cmpxchg implementation
parents 67eacd61 17242086

arch/arm64/include/asm/atomic_lse.h

+5 −12
Original line number Diff line number Diff line
@@ -251,22 +251,15 @@ __lse__cmpxchg_case_##name##sz(volatile void *ptr, \ 
					      u##sz old,		\

					      u##sz new)		\

{									\

	register unsigned long x0 asm ("x0") = (unsigned long)ptr;	\

	register u##sz x1 asm ("x1") = old;				\

	register u##sz x2 asm ("x2") = new;				\

	unsigned long tmp;						\

									\

	asm volatile(							\

	__LSE_PREAMBLE							\

	"	mov	%" #w "[tmp], %" #w "[old]\n"			\

	"	cas" #mb #sfx "\t%" #w "[tmp], %" #w "[new], %[v]\n"	\

	"	mov	%" #w "[ret], %" #w "[tmp]"			\

	: [ret] "+r" (x0), [v] "+Q" (*(u##sz *)ptr),			\

	  [tmp] "=&r" (tmp)						\

	: [old] "r" (x1), [new] "r" (x2)				\

	"	cas" #mb #sfx "	%" #w "[old], %" #w "[new], %[v]\n"	\

	: [v] "+Q" (*(u##sz *)ptr),					\

	  [old] "+r" (old)						\

	: [new] "rZ" (new)						\

	: cl);								\

									\

	return x0;							\

	return old;							\

}



__CMPXCHG_CASE(w, b,     ,  8,   )

arch/arm64/include/asm/barrier.h

+5 −5
Original line number Diff line number Diff line
@@ -131,25 +131,25 @@ do { \ 
	case 1:								\

		asm volatile ("stlrb %w1, %0"				\

				: "=Q" (*__p)				\

				: "r" (*(__u8 *)__u.__c)		\

				: "rZ" (*(__u8 *)__u.__c)		\

				: "memory");				\

		break;							\

	case 2:								\

		asm volatile ("stlrh %w1, %0"				\

				: "=Q" (*__p)				\

				: "r" (*(__u16 *)__u.__c)		\

				: "rZ" (*(__u16 *)__u.__c)		\

				: "memory");				\

		break;							\

	case 4:								\

		asm volatile ("stlr %w1, %0"				\

				: "=Q" (*__p)				\

				: "r" (*(__u32 *)__u.__c)		\

				: "rZ" (*(__u32 *)__u.__c)		\

				: "memory");				\

		break;							\

	case 8:								\

		asm volatile ("stlr %1, %0"				\

		asm volatile ("stlr %x1, %0"				\

				: "=Q" (*__p)				\

				: "r" (*(__u64 *)__u.__c)		\

				: "rZ" (*(__u64 *)__u.__c)		\

				: "memory");				\

		break;							\

	}								\

arch/arm64/include/asm/uaccess.h

+2 −2
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ static inline void __user *__uaccess_mask_ptr(const void __user *ptr) 
	"1:	" load "	" reg "1, [%2]\n"			\

	"2:\n"								\

	_ASM_EXTABLE_##type##ACCESS_ERR_ZERO(1b, 2b, %w0, %w1)		\

	: "+r" (err), "=&r" (x)						\

	: "+r" (err), "=r" (x)						\

	: "r" (addr))



#define __raw_get_mem(ldr, x, ptr, err, type)					\
@@ -327,7 +327,7 @@ do { \ 
	"2:\n"								\

	_ASM_EXTABLE_##type##ACCESS_ERR(1b, 2b, %w0)			\

	: "+r" (err)							\

	: "r" (x), "r" (addr))

	: "rZ" (x), "r" (addr))



#define __raw_put_mem(str, x, ptr, err, type)					\

do {										\