Commit 0f596945 authored by Shravan Kumar Ramani's avatar Shravan Kumar Ramani Committed by Hans de Goede
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platform/mellanox: mlxbf-pmc: Fix reading of unprogrammed events 



This fix involves 2 changes:
 - All event regs have a reset value of 0, which is not a valid
   event_number as per the event_list for most blocks and hence seen
   as an error. Add a "disable" event with event_number 0 for all blocks.

 - The enable bit for each counter need not be checked before
   reading the event info, and hence removed.

Fixes: 1a218d31 ("platform/mellanox: mlxbf-pmc: Add Mellanox BlueField PMC driver")
Signed-off-by: default avatarShravan Kumar Ramani <shravankr@nvidia.com>
Reviewed-by: default avatarVadim Pasternak <vadimp@nvidia.com>
Reviewed-by: default avatarDavid Thompson <davthompson@nvidia.com>
Link: https://lore.kernel.org/r/04d0213932d32681de1c716b54320ed894e52425.1693917738.git.shravankr@nvidia.com


Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent 80ccd405

drivers/platform/mellanox/mlxbf-pmc.c

+7 −20
Original line number Diff line number Diff line
@@ -191,6 +191,7 @@ static const struct mlxbf_pmc_events mlxbf_pmc_smgen_events[] = { 
};



static const struct mlxbf_pmc_events mlxbf_pmc_trio_events_1[] = {

	{ 0x0, "DISABLE" },

	{ 0xa0, "TPIO_DATA_BEAT" },

	{ 0xa1, "TDMA_DATA_BEAT" },

	{ 0xa2, "MAP_DATA_BEAT" },
@@ -214,6 +215,7 @@ static const struct mlxbf_pmc_events mlxbf_pmc_trio_events_1[] = { 
};



static const struct mlxbf_pmc_events mlxbf_pmc_trio_events_2[] = {

	{ 0x0, "DISABLE" },

	{ 0xa0, "TPIO_DATA_BEAT" },

	{ 0xa1, "TDMA_DATA_BEAT" },

	{ 0xa2, "MAP_DATA_BEAT" },
@@ -246,6 +248,7 @@ static const struct mlxbf_pmc_events mlxbf_pmc_trio_events_2[] = { 
};



static const struct mlxbf_pmc_events mlxbf_pmc_ecc_events[] = {

	{ 0x0, "DISABLE" },

	{ 0x100, "ECC_SINGLE_ERROR_CNT" },

	{ 0x104, "ECC_DOUBLE_ERROR_CNT" },

	{ 0x114, "SERR_INJ" },
@@ -258,6 +261,7 @@ static const struct mlxbf_pmc_events mlxbf_pmc_ecc_events[] = { 
};



static const struct mlxbf_pmc_events mlxbf_pmc_mss_events[] = {

	{ 0x0, "DISABLE" },

	{ 0xc0, "RXREQ_MSS" },

	{ 0xc1, "RXDAT_MSS" },

	{ 0xc2, "TXRSP_MSS" },
@@ -265,6 +269,7 @@ static const struct mlxbf_pmc_events mlxbf_pmc_mss_events[] = { 
};



static const struct mlxbf_pmc_events mlxbf_pmc_hnf_events[] = {

	{ 0x0, "DISABLE" },

	{ 0x45, "HNF_REQUESTS" },

	{ 0x46, "HNF_REJECTS" },

	{ 0x47, "ALL_BUSY" },
@@ -323,6 +328,7 @@ static const struct mlxbf_pmc_events mlxbf_pmc_hnf_events[] = { 
};



static const struct mlxbf_pmc_events mlxbf_pmc_hnfnet_events[] = {

	{ 0x0, "DISABLE" },

	{ 0x12, "CDN_REQ" },

	{ 0x13, "DDN_REQ" },

	{ 0x14, "NDN_REQ" },
@@ -892,7 +898,7 @@ static int mlxbf_pmc_read_event(int blk_num, uint32_t cnt_num, bool is_l3, 
				uint64_t *result)

{

	uint32_t perfcfg_offset, perfval_offset;

	uint64_t perfmon_cfg, perfevt, perfctl;

	uint64_t perfmon_cfg, perfevt;



	if (cnt_num >= pmc->block[blk_num].counters)

		return -EINVAL;
@@ -904,25 +910,6 @@ static int mlxbf_pmc_read_event(int blk_num, uint32_t cnt_num, bool is_l3, 
	perfval_offset = perfcfg_offset +

			 pmc->block[blk_num].counters * MLXBF_PMC_REG_SIZE;



	/* Set counter in "read" mode */

	perfmon_cfg = FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_ADDR,

				 MLXBF_PMC_PERFCTL);

	perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_STROBE, 1);

	perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WR_R_B, 0);



	if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + perfcfg_offset,

			    MLXBF_PMC_WRITE_REG_64, perfmon_cfg))

		return -EFAULT;



	/* Check if the counter is enabled */



	if (mlxbf_pmc_read(pmc->block[blk_num].mmio_base + perfval_offset,

			   MLXBF_PMC_READ_REG_64, &perfctl))

		return -EFAULT;



	if (!FIELD_GET(MLXBF_PMC_PERFCTL_EN0, perfctl))

		return -EINVAL;



	/* Set counter in "read" mode */

	perfmon_cfg = FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_ADDR,

				 MLXBF_PMC_PERFEVT);