Commit 0f4b5842 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/dp: add drm_dp_128b132b_read_aux_rd_interval() 



The DP 2.0 errata changes DP_128B132B_TRAINING_AUX_RD_INTERVAL (DPCD
0x2216) completely. Add a new function to read that. Follow-up will need
to clean up existing functions.

v2: fix reversed interpretation of bit 7 meaning (Uma)

Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: default avatarThomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/22f6637194c9edb22b6a84be82dd385550dbb958.1643878928.git.jani.nikula@intel.com
parent f7bc440b

drivers/gpu/drm/drm_dp_helper.c

+20 −0
Original line number Diff line number Diff line
@@ -281,6 +281,26 @@ int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIV 
}

EXPORT_SYMBOL(drm_dp_read_channel_eq_delay);



/* Per DP 2.0 Errata */

int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux)

{

	int unit;

	u8 val;



	if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) != 1) {

		drm_err(aux->drm_dev, "%s: failed rd interval read\n",

			aux->name);

		/* default to max */

		val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;

	}



	unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2;

	val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;



	return (val + 1) * unit * 1000;

}

EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval);



void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,

					    const u8 dpcd[DP_RECEIVER_CAP_SIZE])

{

include/drm/drm_dp_helper.h

+3 −0
Original line number Diff line number Diff line
@@ -1115,6 +1115,7 @@ struct drm_panel; 
# define DP_UHBR13_5                           (1 << 2)



#define DP_128B132B_TRAINING_AUX_RD_INTERVAL                    0x2216 /* 2.0 */

# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT          (1 << 7)

# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK              0x7f

# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US            0x00

# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS              0x01
@@ -1552,6 +1553,8 @@ void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 
void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,

					      const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);



int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);



u8 drm_dp_link_rate_to_bw_code(int link_rate);

int drm_dp_bw_code_to_link_rate(u8 link_bw);