Commit 0f1decaa authored by Sai Prakash Ranjan's avatar Sai Prakash Ranjan Committed by Bjorn Andersson
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arm64: dts: qcom: sc7180: Support ETMv4 power management 



Now that deep idle states are properly supported on SC7180,
we need to add "coresight-loses-context-with-cpu" property
to avoid failure of trace session because of losing context
on entering deep idle states.

Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Signed-off-by: default avatarSai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/20200424111644.27970-1-saiprakash.ranjan@codeaurora.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 0d1ce0d1

arch/arm64/boot/dts/qcom/sc7180.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -1629,6 +1629,7 @@ 


			clocks = <&aoss_qmp>;

			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;



			out-ports {

				port {
@@ -1655,6 +1656,7 @@ 


			clocks = <&aoss_qmp>;

			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;



			out-ports {

				port {
@@ -1673,6 +1675,7 @@ 


			clocks = <&aoss_qmp>;

			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;



			out-ports {

				port {
@@ -1691,6 +1694,7 @@ 


			clocks = <&aoss_qmp>;

			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;



			out-ports {

				port {
@@ -1709,6 +1713,7 @@ 


			clocks = <&aoss_qmp>;

			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;



			out-ports {

				port {
@@ -1727,6 +1732,7 @@ 


			clocks = <&aoss_qmp>;

			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;



			out-ports {

				port {
@@ -1745,6 +1751,7 @@ 


			clocks = <&aoss_qmp>;

			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;



			out-ports {

				port {
@@ -1763,6 +1770,7 @@ 


			clocks = <&aoss_qmp>;

			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;



			out-ports {

				port {