Unverified Commit 0f07963f authored Jul 18, 2024 by openeuler-ci-bot Committed by Gitee Jul 18, 2024

!10095 CVE-2024-40968

Merge Pull Request from: @ci-robot 
 
PR sync from: Liao Chen <liaochen4@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/BB4UF6L3GODHAKZQWOJC6V5PRQWEJVGO/ 
MIPS: Octeon: Add PCIe link status check

Songyang Li (1):
  MIPS: Octeon: Add PCIe link status check


-- 
2.34.1
 
https://gitee.com/src-openeuler/kernel/issues/IACSM3 
 
Link:https://gitee.com/openeuler/kernel/pulls/10095

 

Reviewed-by: Zhang Jianhua <chris.zjh@huawei.com>
Reviewed-by: Zhang Changzhong <zhangchangzhong@huawei.com>
Signed-off-by: Zhang Changzhong <zhangchangzhong@huawei.com>

parents 2c75e3e9 7a7a0820

arch/mips/pci/pcie-octeon.c

100644 → 100755

+6 −0

Original line number	Diff line number	Diff line
		@@ -230,12 +230,18 @@ static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
		{
		union cvmx_pcie_address pcie_addr;
		union cvmx_pciercx_cfg006 pciercx_cfg006;
		union cvmx_pciercx_cfg032 pciercx_cfg032;

		pciercx_cfg006.u32 =
		cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
		if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
		return 0;

		pciercx_cfg032.u32 =
		cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
		if ((pciercx_cfg032.s.dlla == 0) \|\| (pciercx_cfg032.s.lt == 1))
		return 0;

		pcie_addr.u64 = 0;
		pcie_addr.config.upper = 2;
		pcie_addr.config.io = 1;