Unverified Commit 0f0294a6 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!12288 [OLK-6.6] AMD Turin perf vendor event patches

Merge Pull Request from: @PrithivishS 
 
*Description:*
---------------------------------------
Patches to support perf vendor events and tracepoints on Turin systems.

x86/mce: Clean up TP_printk() output line of the 'mce_record' tracepoint

tracing: Add the ::ppin field to the mce_record tracepoint

tracing: Add the ::microcode field to the mce_record tracepoint

perf vendor events amd: Add Zen 5 core events

perf vendor events amd: Add Zen 5 uncore events

perf vendor events amd: Add Zen 5 metrics

perf vendor events amd: Add Zen 5 mapping

All the commits have been system tested and, in addition, a sample of perf events can be tested as follows:- 

 **Without Vendor Event Patches**
```javascript 
$>perf stat -e l3_lookup_state.l3_miss ./test_cache_misses
event syntax error: 'l3_lookup_state.l3_miss'
                     \___ Bad event name
 
Unable to find event on a PMU of 'l3_lookup_state.l3_miss'
Run 'perf list' for a list of valid events
 
Usage: perf stat [<options>] [<command>] 
 
    -e, --event <event>   event selector. use 'perf list' to list available events
``` 
 **With Vendor Event Patches** 
```javascript
$>perf stat -e l3_lookup_state.l3_miss ./test_cache_misses
 
Performance counter stats for 'system wide':
 
            93,616      l3_lookup_state.l3_miss
 
       0.001563242 seconds time elapsed
```

 **Without Vendor Event Patches** 
```javascript
$> perf stat -e bp_l1_tlb_miss_l2_tlb_hit sleep 1
event syntax error: 'bp_l1_tlb_miss_l2_tlb_hit'
                     \___ Bad event name
 
Unable to find event on a PMU of 'bp_l1_tlb_miss_l2_tlb_hit'
Run 'perf list' for a list of valid events
 
" > Usage: perf stat [<options>] [<command>] "
 
    -e, --event <event>   event selector. use 'perf list' to list available events
``` 
 **With Vendor Event Patches** 
```javascript
$>perf stat -e bp_l1_tlb_miss_l2_tlb_hit sleep 1
 
Performance counter stats for 'sleep 1':
 
                 0      bp_l1_tlb_miss_l2_tlb_hit:u
 
       1.001173665 seconds time elapsed
 
       0.001009000 seconds user
       0.000000000 seconds sys
```

 **Without Vendor Event Patches** 
```javascript
$>perf stat -e ls_not_halted_cyc ./test_dispatch_slots
event syntax error: 'ls_not_halted_cyc'
                     \___ Bad event name
 
Unable to find event on a PMU of 'ls_not_halted_cyc'
Run 'perf list' for a list of valid events
 
> Usage: perf stat [<options>] [<command>]
 
    -e, --event <event>   event selector. use 'perf list' to list available events
```
 **With Vendor Event Patches** 
```javascript 
$>perf stat -e ls_not_halted_cyc ./test_dispatch_slots
 
Performance counter stats for './test_dispatch_slots':
 
       147,532,695      ls_not_halted_cyc
 
       0.046021315 seconds time elapsed
 
       0.044920000 seconds user
       0.000999000 seconds sys
```


 
 
Link:https://gitee.com/openeuler/kernel/pulls/12288

 

Reviewed-by: default avatarXu Kuohai <xukuohai@huawei.com>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
parents 173c4b64 699bdfb7
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+21 −4
Original line number Diff line number Diff line
@@ -9,6 +9,14 @@
#include <linux/tracepoint.h>
#include <asm/mce.h>

/*
 * MCE Event Record.
 *
 * Only very relevant and transient information which cannot be
 * gathered from a system by any other means or which can only be
 * acquired arduously should be added to this record.
 */

TRACE_EVENT(mce_record,

	TP_PROTO(struct mce *m),
@@ -25,6 +33,7 @@ TRACE_EVENT(mce_record,
		__field(	u64,		ipid		)
		__field(	u64,		ip		)
		__field(	u64,		tsc		)
		__field(	u64,		ppin		)
		__field(	u64,		walltime	)
		__field(	u32,		cpu		)
		__field(	u32,		cpuid		)
@@ -33,6 +42,7 @@ TRACE_EVENT(mce_record,
		__field(	u8,		cs		)
		__field(	u8,		bank		)
		__field(	u8,		cpuvendor	)
		__field(	u32,		microcode	)
	),

	TP_fast_assign(
@@ -45,6 +55,7 @@ TRACE_EVENT(mce_record,
		__entry->ipid		= m->ipid;
		__entry->ip		= m->ip;
		__entry->tsc		= m->tsc;
		__entry->ppin		= m->ppin;
		__entry->walltime	= m->time;
		__entry->cpu		= m->extcpu;
		__entry->cpuid		= m->cpuid;
@@ -53,20 +64,26 @@ TRACE_EVENT(mce_record,
		__entry->cs		= m->cs;
		__entry->bank		= m->bank;
		__entry->cpuvendor	= m->cpuvendor;
		__entry->microcode	= m->microcode;
	),

	TP_printk("CPU: %d, MCGc/s: %llx/%llx, MC%d: %016Lx, IPID: %016Lx, ADDR/MISC/SYND: %016Lx/%016Lx/%016Lx, RIP: %02x:<%016Lx>, TSC: %llx, PROCESSOR: %u:%x, TIME: %llu, SOCKET: %u, APIC: %x",
	TP_printk("CPU: %d, MCGc/s: %llx/%llx, MC%d: %016Lx, IPID: %016Lx, ADDR: %016Lx, MISC: %016Lx, SYND: %016Lx, RIP: %02x:<%016Lx>, TSC: %llx, PPIN: %llx, vendor: %u, CPUID: %x, time: %llu, socket: %u, APIC: %x, microcode: %x",
		__entry->cpu,
		__entry->mcgcap, __entry->mcgstatus,
		__entry->bank, __entry->status,
		__entry->ipid,
		__entry->addr, __entry->misc, __entry->synd,
		__entry->addr,
		__entry->misc,
		__entry->synd,
		__entry->cs, __entry->ip,
		__entry->tsc,
		__entry->cpuvendor, __entry->cpuid,
		__entry->ppin,
		__entry->cpuvendor,
		__entry->cpuid,
		__entry->walltime,
		__entry->socketid,
		__entry->apicid)
		__entry->apicid,
		__entry->microcode)
);

#endif /* _TRACE_MCE_H */
+93 −0
Original line number Diff line number Diff line
[
  {
    "EventName": "bp_l1_tlb_miss_l2_tlb_hit",
    "EventCode": "0x84",
    "BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
  },
  {
    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",
    "EventCode": "0x85",
    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages.",
    "UMask": "0x01"
  },
  {
    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",
    "EventCode": "0x85",
    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages.",
    "UMask": "0x02"
  },
  {
    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",
    "EventCode": "0x85",
    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages.",
    "UMask": "0x04"
  },
  {
    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k",
    "EventCode": "0x85",
    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
    "UMask": "0x08"
  },
  {
    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.all",
    "EventCode": "0x85",
    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes.",
    "UMask": "0x0f"
  },
  {
    "EventName": "bp_l2_btb_correct",
    "EventCode": "0x8b",
    "BriefDescription": "L2 branch prediction overrides existing prediction (speculative)."
  },
  {
    "EventName": "bp_dyn_ind_pred",
    "EventCode": "0x8e",
    "BriefDescription": "Dynamic indirect predictions (branch used the indirect predictor to make a prediction)."
  },
  {
    "EventName": "bp_de_redirect",
    "EventCode": "0x91",
    "BriefDescription": "Number of times an early redirect is sent to branch predictor. This happens when either the decoder or dispatch logic is able to detect that the branch predictor needs to be redirected."
  },
  {
    "EventName": "bp_l1_tlb_fetch_hit.if4k",
    "EventCode": "0x94",
    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
    "UMask": "0x01"
  },
  {
    "EventName": "bp_l1_tlb_fetch_hit.if2m",
    "EventCode": "0x94",
    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.",
    "UMask": "0x02"
  },
  {
    "EventName": "bp_l1_tlb_fetch_hit.if1g",
    "EventCode": "0x94",
    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.",
    "UMask": "0x04"
  },
  {
    "EventName": "bp_l1_tlb_fetch_hit.all",
    "EventCode": "0x94",
    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",
    "UMask": "0x07"
  },
  {
    "EventName": "bp_redirects.resync",
    "EventCode": "0x9f",
    "BriefDescription": "Redirects of the branch predictor caused by resyncs.",
    "UMask": "0x01"
  },
  {
    "EventName": "bp_redirects.ex_redir",
    "EventCode": "0x9f",
    "BriefDescription": "Redirects of the branch predictor caused by mispredicts.",
    "UMask": "0x02"
  },
  {
    "EventName": "bp_redirects.all",
    "EventCode": "0x9f",
    "BriefDescription": "Redirects of the branch predictor."
  }
]
+115 −0
Original line number Diff line number Diff line
[
  {
    "EventName": "de_op_queue_empty",
    "EventCode": "0xa9",
    "BriefDescription": "Cycles where the op queue is empty. Such cycles indicate that the front-end is not delivering instructions fast enough."
  },
  {
    "EventName": "de_src_op_disp.x86_decoder",
    "EventCode": "0xaa",
    "BriefDescription": "Ops dispatched from x86 decoder.",
    "UMask": "0x01"
  },
  {
    "EventName": "de_src_op_disp.op_cache",
    "EventCode": "0xaa",
    "BriefDescription": "Ops dispatched from op cache.",
    "UMask": "0x02"
  },
  {
    "EventName": "de_src_op_disp.all",
    "EventCode": "0xaa",
    "BriefDescription": "Ops dispatched from any source.",
    "UMask": "0x07"
  },
  {
    "EventName": "de_dis_ops_from_decoder.any_fp_dispatch",
    "EventCode": "0xab",
    "BriefDescription": "Number of ops dispatched to the floating-point unit.",
    "UMask": "0x04"
  },
  {
    "EventName": "de_dis_ops_from_decoder.any_integer_dispatch",
    "EventCode": "0xab",
    "BriefDescription": "Number of ops dispatched to the integer execution unit.",
    "UMask": "0x08"
  },
  {
    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.int_phy_reg_file_rsrc_stall",
    "EventCode": "0xae",
    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to an integer physical register file resource stall.",
    "UMask": "0x01"
  },
  {
    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.load_queue_rsrc_stall",
    "EventCode": "0xae",
    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a lack of load queue tokens.",
    "UMask": "0x02"
  },
  {
    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.store_queue_rsrc_stall",
    "EventCode": "0xae",
    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a lack of store queue tokens.",
    "UMask": "0x04"
  },
  {
    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.taken_brnch_buffer_rsrc",
    "EventCode": "0xae",
    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a taken branch buffer resource stall.",
    "UMask": "0x10"
  },
  {
    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.fp_sch_rsrc_stall",
    "EventCode": "0xae",
    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a floating-point non-schedulable queue token stall.",
    "UMask": "0x40"
  },
  {
    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.al_tokens",
    "EventCode": "0xaf",
    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of ALU tokens.",
    "UMask": "0x01"
  },
  {
    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.ag_tokens",
    "EventCode": "0xaf",
    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of agen tokens.",
    "UMask": "0x02"
  },
  {
    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.ex_flush_recovery",
    "EventCode": "0xaf",
    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a pending integer execution flush recovery.",
    "UMask": "0x04"
  },
  {
    "EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.retq",
    "EventCode": "0xaf",
    "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of retire queue tokens.",
    "UMask": "0x20"
  },
  {
    "EventName": "de_no_dispatch_per_slot.no_ops_from_frontend",
    "EventCode": "0x1a0",
    "BriefDescription": "In each cycle counts dispatch slots left empty because the front-end did not supply ops.",
    "UMask": "0x01"
  },
  {
    "EventName": "de_no_dispatch_per_slot.backend_stalls",
    "EventCode": "0x1a0",
    "BriefDescription": "In each cycle counts ops unable to dispatch because of back-end stalls.",
    "UMask": "0x1e"
  },
  {
    "EventName": "de_no_dispatch_per_slot.smt_contention",
    "EventCode": "0x1a0",
    "BriefDescription": "In each cycle counts ops unable to dispatch because the dispatch cycle was granted to the other SMT thread.",
    "UMask": "0x60"
  },
  {
    "EventName": "de_additional_resource_stalls.dispatch_stalls",
    "EventCode": "0x1a2",
    "BriefDescription": "Counts additional cycles where dispatch is stalled due to a lack of dispatch resources.",
    "UMask": "0x30"
  }
]
+174 −0
Original line number Diff line number Diff line
[
  {
    "EventName": "ex_ret_instr",
    "EventCode": "0xc0",
    "BriefDescription": "Retired instructions."
  },
  {
    "EventName": "ex_ret_ops",
    "EventCode": "0xc1",
    "BriefDescription": "Retired macro-ops."
  },
  {
    "EventName": "ex_ret_brn",
    "EventCode": "0xc2",
    "BriefDescription": "Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
  },
  {
    "EventName": "ex_ret_brn_misp",
    "EventCode": "0xc3",
    "BriefDescription": "Retired branch instructions mispredicted."
  },
  {
    "EventName": "ex_ret_brn_tkn",
    "EventCode": "0xc4",
    "BriefDescription": "Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
  },
  {
    "EventName": "ex_ret_brn_tkn_misp",
    "EventCode": "0xc5",
    "BriefDescription": "Retired taken branch instructions mispredicted."
  },
  {
    "EventName": "ex_ret_brn_far",
    "EventCode": "0xc6",
    "BriefDescription": "Retired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction."
  },
  {
    "EventName": "ex_ret_near_ret",
    "EventCode": "0xc8",
    "BriefDescription": "Retired near returns (RET or RET Iw)."
  },
  {
    "EventName": "ex_ret_near_ret_mispred",
    "EventCode": "0xc9",
    "BriefDescription": "Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
  },
  {
    "EventName": "ex_ret_brn_ind_misp",
    "EventCode": "0xca",
    "BriefDescription": "Retired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
  },
  {
    "EventName": "ex_ret_mmx_fp_instr.x87",
    "EventCode": "0xcb",
    "BriefDescription": "Retired x87 instructions.",
    "UMask": "0x01"
  },
  {
    "EventName": "ex_ret_mmx_fp_instr.mmx",
    "EventCode": "0xcb",
    "BriefDescription": "Retired MMX instructions.",
    "UMask": "0x02"
  },
  {
    "EventName": "ex_ret_mmx_fp_instr.sse",
    "EventCode": "0xcb",
    "BriefDescription": "Retired SSE instructions (includes SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42 and AVX).",
    "UMask": "0x04"
  },
  {
    "EventName": "ex_ret_ind_brch_instr",
    "EventCode": "0xcc",
    "BriefDescription": "Retired indirect branch instructions."
  },
  {
    "EventName": "ex_ret_cond",
    "EventCode": "0xd1",
    "BriefDescription": "Retired conditional branch instructions."
  },
  {
    "EventName": "ex_div_busy",
    "EventCode": "0xd3",
    "BriefDescription": "Number of cycles the divider is busy."
  },
  {
    "EventName": "ex_div_count",
    "EventCode": "0xd4",
    "BriefDescription": "Divide ops executed."
  },
  {
    "EventName": "ex_no_retire.empty",
    "EventCode": "0xd6",
    "BriefDescription": "Cycles with no retire due  to the lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects).",
    "UMask": "0x01"
  },
  {
    "EventName": "ex_no_retire.not_complete",
    "EventCode": "0xd6",
    "BriefDescription": "Cycles with no retire while the oldest op is waiting to be executed.",
    "UMask": "0x02"
  },
  {
    "EventName": "ex_no_retire.other",
    "EventCode": "0xd6",
    "BriefDescription": "Cycles with no retire caused by other reasons (retire breaks, traps, faults, etc.).",
    "UMask": "0x08"
  },
  {
    "EventName": "ex_no_retire.thread_not_selected",
    "EventCode": "0xd6",
    "BriefDescription": "Cycles with no retire because thread arbitration did not select the thread.",
    "UMask": "0x10"
  },
  {
    "EventName": "ex_no_retire.load_not_complete",
    "EventCode": "0xd6",
    "BriefDescription": "Cycles with no retire while the oldest op is waiting for load data.",
    "UMask": "0xa2"
  },
  {
    "EventName": "ex_no_retire.all",
    "EventCode": "0xd6",
    "BriefDescription": "Cycles with no retire for any reason.",
    "UMask": "0x1b"
  },
  {
    "EventName": "ex_ret_ucode_instr",
    "EventCode": "0x1c1",
    "BriefDescription": "Retired microcoded instructions."
  },
  {
    "EventName": "ex_ret_ucode_ops",
    "EventCode": "0x1c2",
    "BriefDescription": "Retired microcode ops."
  },
  {
    "EventName": "ex_ret_msprd_brnch_instr_dir_msmtch",
    "EventCode": "0x1c7",
    "BriefDescription": "Retired branch instructions mispredicted due to direction mismatch."
  },
  {
    "EventName": "ex_ret_uncond_brnch_instr_mispred",
    "EventCode": "0x1c8",
    "BriefDescription": "Retired unconditional indirect branch instructions mispredicted."
  },
  {
    "EventName": "ex_ret_uncond_brnch_instr",
    "EventCode": "0x1c9",
    "BriefDescription": "Retired unconditional branch instructions."
  },
  {
    "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
    "EventCode": "0x1cf",
    "BriefDescription": "Ops tagged by IBS.",
    "UMask": "0x01"
  },
  {
    "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
    "EventCode": "0x1cf",
    "BriefDescription": "Ops tagged by IBS that retired.",
    "UMask": "0x02"
  },
  {
    "EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
    "EventCode": "0x1cf",
    "BriefDescription": "Ops not tagged by IBS due to a previous tagged op that has not yet signaled interrupt.",
    "UMask": "0x04"
  },
  {
    "EventName": "ex_ret_fused_instr",
    "EventCode": "0x1d0",
    "BriefDescription": "Retired fused instructions."
  }
]
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