Commit 0ef99f82 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Stephen Boyd
Browse files

clk: at91: clk-master: fix prescaler logic 



When prescaler value read from register is MASTER_PRES_MAX it means
that the input clock will be divided by 3. Fix the code to reflect
this.

Fixes: 7a110b91 ("clk: at91: clk-master: re-factor master clock")
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-11-claudiu.beznea@microchip.com


Acked-by: default avatarNicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent a27748ad

drivers/clk/at91/clk-master.c

+1 −1
Original line number Diff line number Diff line
@@ -386,7 +386,7 @@ static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, 


	val &= master->layout->mask;

	pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;

	if (pres == 3 && characteristics->have_div3_pres)

	if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres)

		pres = 3;

	else

		pres = (1 << pres);